Henry Duwe

Orcid: 0000-0003-2310-7399

According to our database1, Henry Duwe authored at least 31 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Lure: A simulator for networks of batteryless intermittent nodes.
Perform. Evaluation, 2024

2023
RF Energy Harvester with Constant Off-Time Charger for Batteryless Devices.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Case Studies in Applying Design Thinking to Course Design in Computer Engineering.
Proceedings of the IEEE Frontiers in Education Conference, 2023

2022
A Tale of Two Intermittencies.
Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems, 2022

Toward a Shared Sense of Time for a Network of Batteryless, Intermittently-powered Nodes.
Proceedings of the IEEE International Performance, 2022

Defining and Supporting a Debugging Mindset in Computer Engineering Courses.
Proceedings of the IEEE Frontiers in Education Conference, 2022

2021
Experimental Study of Lifecycle Management Protocols for Batteryless Intermittent Communication.
Proceedings of the IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems, 2021

DENNI: Distributed Neural Network Inference on Severely Resource Constrained Edge Devices.
Proceedings of the IEEE International Performance, 2021

Learning and Professional Development Through Integrated Reflective Activities in Electrical and Computer Engineering Courses.
Proceedings of the IEEE Frontiers in Education Conference, 2021

Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks.
J. Signal Process. Syst., 2020

HARC: A Heterogeneous Array of Redundant Persistent Clocks for Batteryless, Intermittently-Powered Systems.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

Lifecycle Management Protocols for Batteryless, Intermittent Sensor Nodes.
Proceedings of the 39th IEEE International Performance Computing and Communications Conference, 2020

2019
Revisiting Time Remanence Clocks for Energy Harvesting Wireless Sensor Nodes.
Proceedings of the 7th International Workshop on Energy Harvesting & Energy-Neutral Sensing Systems, 2019

An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints.
IEEE Micro, 2018

2017
Dependable design for low-cost ultra-low-power processors
PhD thesis, 2017

Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors.
ACM Trans. Comput. Syst., 2017

Software-based gate-level information flow security for IoT systems.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Enabling Effective Module-Oblivious Power Gating for Embedded Processors.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Bit Serializing a Microprocessor for Ultra-low-power.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

A Unified Framework for Error Correction in On-chip Memories.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

Approximate bitcoin mining.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Correction prediction: Reducing error correction latency for on-chip memories.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Better-Than-Worst-Case Design: Progress and Opportunities.
J. Comput. Sci. Technol., 2014

2013
Modular Design of High-Throughput, Low-Latency Sorting Units.
IEEE Trans. Computers, 2013

High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity.
IEEE Comput. Archit. Lett., 2013

Low-power, low-storage-overhead chipkill correct via multi-line error correction.
Proceedings of the International Conference for High Performance Computing, 2013

Markov chain algorithms: A template for building future robust low power systems.
Proceedings of the 2013 Asilomar Conference on Signals, 2013


  Loading...