Jae Hur

Orcid: 0000-0003-1446-2305

According to our database¹, Jae Hur authored at least 9 papers between 2020 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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Bibliography

2023

Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

2022

Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Nonvolatile Capacitive Crossbar Array for In-Memory Computing.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2022

Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling.

[BibT_eX]

[DOI]

Gihun Choe

Prasanna Venkatesan Ravindran

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2021

A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2021

Compute-in-Memory: From Device Innovation to 3D System Integration.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Experimental RF Characterization of Ferroelectric Hafnium Zirconium Oxide Material at GHz for Microwave Applications.

[BibT_eX]

[DOI]

Proceedings of the Device Research Conference, 2021

2020

Modeling Multi-states in Ferroelectric Tunnel Junction.

[BibT_eX]

[DOI]

Proceedings of the 2020 Device Research Conference, 2020

Jae Hur

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