Yuan-Chun Luo

Orcid: 0000-0001-5793-075X

According to our database1, Yuan-Chun Luo authored at least 11 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
IEEE Trans. Computers, 2022

Nonvolatile Capacitive Crossbar Array for In-Memory Computing.
Adv. Intell. Syst., 2022

2021
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.
Proceedings of the IEEE International Memory Workshop, 2021

A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure.
Proceedings of the IEEE International Memory Workshop, 2021

Compute-in-Memory: From Device Innovation to 3D System Integration.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Modeling Multi-states in Ferroelectric Tunnel Junction.
Proceedings of the 2020 Device Research Conference, 2020

2018
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout.
Proceedings of the 2018 International Symposium on VLSI Design, 2018


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