# Pallab Dasgupta

According to our database

Collaborative distances:

^{1}, Pallab Dasgupta authored at least 158 papers between 1994 and 2019.Collaborative distances:

## Timeline

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## Bibliography

2019

Automatic Characterization of Exploitable Faults: A Machine Learning Approach.

IEEE Trans. Information Forensics and Security, 2019

2018

ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers.

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Formal Feature Interpretation of Hybrid Systems.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers.

IACR Cryptology ePrint Archive, 2018

Co-Synthesis of Loop Execution Patterns for Multihop Control Networks.

Embedded Systems Letters, 2018

Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components.

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

AMS-Miner: Mining AMS Assertions Using Interval Arithmetic.

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Feature Based Coverage Analysis of AMS Circuits.

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Formal Methods for Validation and Test Point Prioritization in Railway Signaling Logic.

IEEE Trans. Intelligent Transportation Systems, 2017

A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control.

ACM Trans. Embedded Comput. Syst., 2017

Differential Fault Analysis Automation.

IACR Cryptology ePrint Archive, 2017

Automatic Characterization of Exploitable Faults: A Machine Learning Approach.

IACR Cryptology ePrint Archive, 2017

Formal Verification of Power Management Logic with Mixed-Signal Domains.

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy.

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs.

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A Framework for Automated Feature Based Mixed-Signal Equivalence Checking.

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

An Automated Framework for Exploitable Fault Identification in Block Ciphers - A Data Mining Approach.

Proceedings of the PROOFS@CHES 2017, 2017

ForFET: A Formal Feature Evaluation Tool for Hybrid Systems.

Proceedings of the Automated Technology for Verification and Analysis, 2017

2016

Feature Indented Assertions for Analog and Mixed-Signal Validation.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Formal assessment of reliability specifications in embedded cyber-physical systems.

J. Applied Logic, 2016

Multirate Sampling for Power-Performance Tradeoff in Embedded Control.

Embedded Systems Letters, 2016

Planning based guided reconstruction of corner cases in architectural validation.

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Formal feature analysis of hybrid automata.

Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

A Robust Non-Parametric and Filtering Based Approach for Glottal Closure Instant Detection.

Proceedings of the Interspeech 2016, 2016

Scheduling of Controllers' Update-Rates for Residual Bandwidth Utilization.

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2016

2015

Automated Planning as an Early Verification Tool for Distributed Control.

J. Autom. Reasoning, 2015

Formal Interpretation of Assertion-Based Features on AMS Designs.

IEEE Design & Test, 2015

Formal Methods for Pattern Based Reliability Analysis in Embedded Systems.

Proceedings of the 28th International Conference on VLSI Design, 2015

Monitoring AMS Simulation: From Assertions to Features.

Proceedings of the 28th International Conference on VLSI Design, 2015

Raga identification based on Normalized Note Histogram features.

Proceedings of the 2015 International Conference on Advances in Computing, 2015

A New Approach for Minimal Environment Construction for Modular Property Verification.

Proceedings of the 24th IEEE Asian Test Symposium, 2015

Timing Analysis of Safety-Critical Automotive Software: The AUTOSAFE Tool Flow.

Proceedings of the 2015 Asia-Pacific Software Engineering Conference, 2015

2014

Formal Hardware/Software Co-Verification of Embedded Power Controllers.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Time-budgeting: a component based development methodology for real-time embedded systems.

Formal Asp. Comput., 2014

Synthesis of sampling modes for adaptive control.

Proceedings of the 2014 IEEE International Conference on Control System, 2014

Acceptance and random generation of event sequences under real time calculus constraints.

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Early Time-Budgeting for Component-Based Embedded Control Systems.

Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

2013

Formal Verification of Architectural Power Intent.

IEEE Trans. VLSI Syst., 2013

Counterexample Ranking Using Mined Invariants.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Formal Guarantees for Localized Bug Fixes.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis.

J. Low Power Electronics, 2013

Post-silicon debugging of PMU integration errors using behavioral models.

Integration, 2013

A fuzzy real-time temporal logic.

Int. J. Approx. Reasoning, 2013

Reliability Guarantees in Automata-Based Scheduling for Embedded Control Software.

Embedded Systems Letters, 2013

Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications.

Embedded Systems Letters, 2013

Model Checking Controllers with Predicate Inputs.

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Formal Verification of Hardware / Software Power Management Strategies.

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Ordered Solution Generation for Implicit AND/OR Search Spaces.

Proceedings of the Pattern Recognition and Machine Intelligence, 2013

Model checking of global power management strategies in software with temporal logic properties.

Proceedings of the 6th India Software Engineering Conference, 2013

Debugging assertion failures in software controllers using a reference model.

Proceedings of the 6th India Software Engineering Conference, 2013

Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures : Extended Abstract.

Proceedings of the IJCAI 2013, 2013

Handling fault detection latencies in automata-based scheduling for embedded control software.

Proceedings of the 2013 IEEE International Symposium on Computer-Aided Control System Design, 2013

2012

Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice.

ACM Trans. Design Autom. Electr. Syst., 2012

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults.

ACM Trans. Design Autom. Electr. Syst., 2012

Computing Minimal Debugging Windows in Failure Traces of AMS Assertions.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Assertion Aware Sampling Refinement: A Mixed-Signal Perspective.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads.

J. Low Power Electronics, 2012

Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures.

J. Artif. Intell. Res., 2012

SAT based timing analysis for fixed and rise/fall gate delay models.

Integration, 2012

Verification by parts: reusing component invariant checking results.

IET Computers & Digital Techniques, 2012

Cohesive Coverage Management: Simulation Meets Formal Methods.

J. Electronic Testing, 2012

A Library for Passive Online Verification of Analog and Mixed-Signal Circuits.

Proceedings of the 25th International Conference on VLSI Design, 2012

Workload Driven Power Domain Partitioning.

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Execution Ordering in AND/OR Graphs with Failure Probabilities.

Proceedings of the Fifth Annual Symposium on Combinatorial Search, 2012

Reliability annotations to formal specifications of context-sensitive safety properties in embedded systems.

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Formal methods for ranking counterexamples through assumption mining.

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Planning with Action Prioritization and New Benchmarks for Classical Planning.

Proceedings of the AI 2012: Advances in Artificial Intelligence, 2012

Anytime Algorithms for Biobjective Heuristic Search.

Proceedings of the AI 2012: Advances in Artificial Intelligence, 2012

A Generalized Theory for Formal Assertion Coverage.

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Formal methods for coverage analysis of architectural power states in power-managed designs.

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture.

Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012

2011

Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models.

ACM Trans. Design Autom. Electr. Syst., 2011

Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

A WLAN security management framework based on formal spatio-temporal RBAC model.

Security and Communication Networks, 2011

Some results on Parametric Temporal Logic.

Inf. Process. Lett., 2011

Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions.

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces.

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Policy Based Security Analysis in Enterprise Networks: A Formal Approach.

IEEE Trans. Network and Service Management, 2010

Bounded delay timing analysis and power estimation using SAT.

Microelectronics Journal, 2010

A static verification approach for architectural integration of mixed-signal integrated circuits.

Integration, 2010

Integrated security analysis framework for an enterprise network - a formal approach.

IET Information Security, 2010

Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Coverage Management with Inline Assertions and Formal Test Points.

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A Spatio-Temporal Role-Based Access Control Model for Wireless LAN Security Policy Management.

Proceedings of the Information Systems, Technology and Management, 2010

Taming the component timing: A CBD methodology for real-time embedded systems.

Proceedings of the Design, Automation and Test in Europe, 2010

Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.

Proceedings of the 47th Design Automation Conference, 2010

Concurrent Usage Control Implementation Verification Using the SPIN Model Checker.

Proceedings of the Recent Trends in Network Security and Applications, 2010

A SAT Based Verification Framework for Wireless LAN Security Policy Management Supported by STRBAC Model.

Proceedings of the Recent Trends in Network Security and Applications, 2010

A Query based Formal Security Analysis Framework for Enterprise LAN.

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009

Design intent coverage revisited.

ACM Trans. Design Autom. Electr. Syst., 2009

Instrumenting AMS assertion verification on commercial platforms.

ACM Trans. Design Autom. Electr. Syst., 2009

Inline Assertions - Embedding Formal Properties in a Test Bench.

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Fault Analysis of Security Policy Implementations in Enterprise Networks.

Proceedings of the First International Conference on Networks and Communications, 2009

Formal Verification of Security Policy Implementations in Enterprise Networks.

Proceedings of the Information Systems Security, 5th International Conference, 2009

A formal approach for specification-driven AMS behavioral model generation.

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Satisfiability Models for Maximum Transition Power.

IEEE Trans. VLSI Syst., 2008

Auxiliary state machines + context-triggered properties in verification.

ACM Trans. Design Autom. Electr. Syst., 2008

Accelerating Assertion Coverage With Adaptive Testbenches.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Cohesive Coverage Management for Simulation and Formal Property Verification.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A Dynamic Assertion-Based Verification Platform for Validation of UML Designs.

Proceedings of the Automated Technology for Verification and Analysis, 2008

CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications.

Proceedings of the Automated Technology for Verification and Analysis, 2008

2007

Event propagation for accurate circuit delay calculation using SAT.

ACM Trans. Design Autom. Electr. Syst., 2007

BUSpec: A framework for generation of verification aids for standard bus protocol specifications.

Integration, 2007

Hardware accelerated constrained random test generation.

IET Computers & Digital Techniques, 2007

Statistical static timing analysis using symbolic event propagation.

IET Circuits, Devices & Systems, 2007

Bounded Delay Timing Analysis Using Boolean Satisfiability.

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation.

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

2006

Design-Intent Coverage - A New Paradigm for Formal Property Verification.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Instruction-Set-Extension Exploration Using Decomposable Heuristic Search.

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Framework for Estimating Peak Power in Gate-Level Circuits.

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Formal methods for checking realizability of coalitions in 3-party systems.

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Synthesis of system verilog assertions.

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

What lies between design intent coverage and model checking?

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Test generation games from formal specifications.

Proceedings of the 43rd Design Automation Conference, 2006

Discovering the input assumptions in specification refinement coverage.

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

The open family of temporal logics: Annotating temporal operators with input constraints.

ACM Trans. Design Autom. Electr. Syst., 2005

Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules.

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

SAT based solutions for consistency problems in formal property specifications for open systems.

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

The power of first-order quantification over states in branching and linear time temporal logics.

Inf. Process. Lett., 2004

Property Refinement Techniques for Enhancing Coverage of Formal Property Verification.

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Formal Verification of Modules under Real Time Environment Constraints.

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

The BUSpec platform for automated generation of verification aids for standard bus protocols.

Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures.

Proceedings of the Distributed Computing, 2004

Formal verification coverage: computing the coverage gap between temporal specifications.

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?

Proceedings of the 2004 Design, 2004

2003

A Branching Time Temporal Framework for Quantitative Reasoning.

J. Autom. Reasoning, 2003

Open computation tree logic with fairness.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques.

IEEE Trans. Knowl. Data Eng., 2002

Quantified Computation Tree Logic.

Inf. Process. Lett., 2002

Open Computation Tree Logic for Formal Verification of Modules.

Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Formal verification of module interfaces against real time specifications.

Proceedings of the 39th Design Automation Conference, 2002

2001

Min-max Computation Tree Logic.

Artif. Intell., 2001

Symbolic verification of Boolean constraints over partially specified functions.

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Abstractions for model checking of event timings.

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Abstraction of word-level linear arithmetic functions from bit-level component descriptions.

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Model checking on timed-event structures.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

1999

An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Controlling State Explosion in Static Simulation by Selective Composition.

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems.

Proceedings of the High Performance Computing, 1999

1998

A Heuristic for the Maximum Processor Requirement for Scheduling Layered Task Graphs with Coloring.

J. Parallel Distrib. Comput., 1998

Agreement under Faulty Interfaces.

Inf. Process. Lett., 1998

1997

V_THR: An Adaptive Load Balancing Algorithm.

J. Parallel Distrib. Comput., 1997

1996

Multiobjektive Heuristic Search in AND/OR Graphs.

J. Algorithms, 1996

Agent Search in Uniform b-Ary Trees: Multiple Goals and Unequal Costs.

Inf. Process. Lett., 1996

Searching Game Trees under a Partial Order.

ICGA Journal, 1996

Searching Game Trees under a Partial Order.

Artif. Intell., 1996

A New Competitive Algorithm for Agent Searching in Unknown Streets.

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1996

1995

Utility of Pathmax in Partial Order Heuristic Search.

Inf. Process. Lett., 1995

A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening".

Artif. Intell., 1995

A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors.

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1995

1994

Agent Searching in a Tree and the Optimality of Iterative Deepening.

ICGA Journal, 1994

Agent Searching in a Tree and the Optimality of Iterative Deepening.

Artif. Intell., 1994

Multiobjective Search in VLSI Design.

Proceedings of the Seventh International Conference on VLSI Design, 1994