Javier Jalle

According to our database, Javier Jalle authored at least 11 papers between 2013 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration.

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla

IEEE Trans. Computers, 2017

2016

Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain.

Javier Jalle

PhD thesis, 2016

Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems.

Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla

Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Contention-aware performance monitoring counte support for real-time MPSoCs.

Javier Jalle, Mikel Fernández, Jaume Abella, Jan Andersson, Mathieu Patte, Luca Fossati, Marco Zulianello, Francisco J. Cazorla

Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems.

David Trilla, Javier Jalle, Mikel Fernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

2015

Resource usage templates and signatures for COTS multicore processors.

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla

Proceedings of the 52nd Annual Design Automation Conference, 2015

Increasing confidence on measurement-based contention bounds for real-time round-robin buses.

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study.

Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla

Proceedings of the IEEE 35th IEEE Real-Time Systems Symposium, 2014

AHRB: A high-performance time-composable AMBA AHB bus.

Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla

Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Bus designs for time-probabilistic multicore processors.

Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Deconstructing bus access control policies for Real-Time multicores.

Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla

Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013