Jeffrey L. Miller

According to our database, Jeffrey L. Miller authored at least 5 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.

Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang

IEEE J. Solid State Circuits, 2016

2015

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.

Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

2^nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.

Mesut Meterelliyoz, Fuad H. Al-amoody, Umut Arslan, Fatih Hamzaoglu, Luke Hood, Manoj B. Lal, Jeffrey L. Miller, Anand Ramasundar, Dan Soltman, Ifar Wan, Yih Wang, Kevin Zhang

Proceedings of the Symposium on VLSI Circuits, 2014

2011

A Family of 32 nm IA Processors.

Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Praveen Mosalikanti, Timothy M. Wilson, Ali M. El-Husseini, Mark Neidengard, Ramy E. Aly, Mahadev Nemani, Muntaquim Chowdhury, Rajesh Kumar

IEEE J. Solid State Circuits, 2011

2010

Westmere: A family of 32nm IA processors.

Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury

Proceedings of the IEEE International Solid-State Circuits Conference, 2010