Mesut Meterelliyoz

According to our database1, Mesut Meterelliyoz authored at least 20 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2019
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 3.6Mb 10.1Mb/mm<sup>2</sup> Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
2<sup>nd</sup> generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2014

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.
IEEE J. Solid State Circuits, 2013

2011
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications.
IEEE Micro, 2008

Thermal analysis of 8-T SRAM for nano-scaled technologies.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A high sensitivity process variation sensor utilizing sub-threshold operation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
A leakage control system for thermal stability during burn-in test.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005


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