Jenlung Liu

According to our database, Jenlung Liu authored at least 3 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

15.2 A 0.012mm² 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.

Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A 0.004mm² 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm² 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.

Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS.

Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011