Jihyun F. Kim

According to our database, Jihyun F. Kim authored at least 13 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

A 0.02mm² fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology.

Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015

PAIDB v2.0: exploration and analysis of pathogenicity and resistance islands.

Sung Ho Yoon, Young-Kyu Park, Jihyun F. Kim

Nucleic Acids Res., 2015

14.8 A 0.009mm² 2.06mW 32-to-2000MHz 2^nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.

Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.

Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 0.010mm² 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology.

Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A 0.032mm² 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.

Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.026mm² 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.

Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 0.004mm² 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm² 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.

Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS.

Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2008

CFGP: a web-based, comparative fungal genomics platform.

Jongsun Park, Bongsoo Park, Kyongyong Jung, Suwang Jang, Kwangyul Yu, Jaeyoung Choi, Sunghyung Kong, Jaejin Park, Seryun Kim, Hyojeong Kim, Soonok Kim, Jihyun F. Kim, Jaime E. Blair, Kwangwon Lee, Seogchan Kang, Yong-Hwan Lee

Nucleic Acids Res., 2008

2007

Towards pathogenomics: a web-based resource for pathogenicity islands.

Sung Ho Yoon, Young-Kyu Park, Soohyun Lee, Doil Choi, Tae Kwang Oh, Cheol-Goo Hur, Jihyun F. Kim

Nucleic Acids Res., 2007

Ensemble learning of genetic networks from time-series expression data.

Dougu Nam, Sung Ho Yoon, Jihyun F. Kim

Bioinform., 2007

2005

A computational approach for identifying pathogenicity islands in prokaryotic genomes.

Sung Ho Yoon, Cheol-Goo Hur, Ho-Young Kang, Yeoun Hee Kim, Tae Kwang Oh, Jihyun F. Kim

BMC Bioinform., 2005