Hojin Park
Orcid: 0009-0005-7057-2455
According to our database1,
Hojin Park
authored at least 36 papers
between 2003 and 2024.
Collaborative distances:
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Bibliography
2024
Pattern Recognit., January, 2024
2023
Proceedings of the 16th ACM International Conference on Systems and Storage, 2023
Minimum Assumption Reconstruction Attacks: Rise of Security and Privacy Threats Against Face Recognition.
Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023
Pretrained Implicit-Ensemble Transformer for Open-Set Authentication on Multimodal Mobile Biometrics.
Proceedings of the 31st ACM International Conference on Multimedia, 2023
Proceedings of the IEEE International Conference on Image Processing, 2023
2022
Proceedings of the 26th International Conference on Pattern Recognition, 2022
2020
An Asynchronous Boost Converter With Time-Based Dual-Mode Control for Wide Load Range and High Efficiency in SSD Applications.
IEEE Trans. Ind. Electron., 2020
Proceedings of the 12th USENIX Workshop on Hot Topics in Cloud Computing, 2020
2019
Proceedings of the 39th IEEE International Conference on Distributed Computing Systems, 2019
Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019
2018
2017
A 0.015-mm<sup>2</sup> Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
2016
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
14.8 A 0.009mm<sup>2</sup> 2.06mW 32-to-2000MHz 2<sup>nd</sup>-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator.
IEEE J. Solid State Circuits, 2014
A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2014
15.2 A 0.012mm<sup>2</sup> 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 0.010mm<sup>2</sup> 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A 0.032mm<sup>2</sup> 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 0.026mm<sup>2</sup> 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 0.004mm<sup>2</sup> 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm<sup>2</sup> 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
IEEE Trans. Consumer Electron., 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2009
IEEE Trans. Consumer Electron., 2009
2008
IEEE Trans. Consumer Electron., 2008
IEEE Trans. Consumer Electron., 2008
2007
Proceedings of the Managing Next Generation Networks and Services, 2007
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003