Taeik Kim

According to our database1, Taeik Kim authored at least 24 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Session 5 Overview: Analog Interfaces Analog Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Session 19 overview: Sensors and interfaces: Analog subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 0.02mm<sup>2</sup> fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017
A 0.015-mm<sup>2</sup> Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique.
IEEE J. Solid State Circuits, 2017

2016
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

14.8 A 0.009mm<sup>2</sup> 2.06mW 32-to-2000MHz 2<sup>nd</sup>-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2014

15.2 A 0.012mm<sup>2</sup> 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 0.010mm<sup>2</sup> 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 0.032mm<sup>2</sup> 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.026mm<sup>2</sup> 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 0.004mm<sup>2</sup> 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm<sup>2</sup> 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2004
Compact model generation for on-chip transmission lines.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A tunable transmission line phase shifter (TTPS).
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
On-chip inductor structures: a comparative study.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Accurate compact model extraction for on-chip coplanar waveguides.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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