Jens-Peter Kaps

Orcid: 0000-0002-7036-6433

Affiliations:
  • George Mason University, Fairfax VA, USA


According to our database1, Jens-Peter Kaps authored at least 50 papers between 1998 and 2023.

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Bibliography

2023
SCA Evaluation and Benchmarking of Finalists in the NIST Lightweight Cryptography Standardization Process.
IACR Cryptol. ePrint Arch., 2023

FOBOS 3: An Open-Source Platform for Side-Channel Analysis and Benchmarking.
Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security, 2023

2022
Enhancing Information Security Courses With a Remotely Accessible Side-Channel Analysis Setup.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
A Lightweight Implementation of Saber Resistant Against Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2021

Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: Methodology, Metrics, Tools, and Results.
IACR Cryptol. ePrint Arch., 2020

Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2019
A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography.
IACR Cryptol. ePrint Arch., 2019

Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon.
IACR Cryptol. ePrint Arch., 2019

Vulnerability Analysis of a Soft Core Processor through Fine-grain Power Profiling.
IACR Cryptol. ePrint Arch., 2019

An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

2018
Improved Lightweight Implementations of CAESAR Authenticated Ciphers.
IACR Cryptol. ePrint Arch., 2018

Comparison of Cost of Protection against Differential Power Analysis of Selected Authenticated Ciphers.
Cryptogr., 2018

Comparing the Cost of Protecting Selected Lightweight Block Ciphers against Differential Power Analysis in Low-Cost FPGAs.
Comput., 2018

Experimental Power and Performance Evaluation of CAESAR Hardware Finalists.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Face-off Between the CAESAR Lightweight Finalists: ACORN vs. Ascon.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Fixing the CLOC with Fine-grain Leakage Analysis.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

2017
Implementation of efficient SR-Latch PUF on FPGA and SoC devices.
Microprocess. Microsystems, 2017

Evaluation of the CAESAR hardware API for lightweight implementations.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Side-channel resistant soft core processor for lightweight block ciphers.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption.
Proceedings of the International Conference on Field Programmable Technology, 2017

Comparison of hardware and software implementations of selected lightweight block ciphers.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
CAESAR Hardware API.
IACR Cryptol. ePrint Arch., 2016

An area-optimized serial implementation of ICEPOLE authenticated encryption schemes.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
Comparison of multi-purpose cores of Keccak and AES.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficient SR-Latch PUF.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2013
Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling Techniques.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

FPGA PUF Based on Programmable LUT Delays.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2011
Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Lightweight Implementations of SHA-3 Candidates on FPGAs.
Proceedings of the Progress in Cryptology - INDOCRYPT 2011, 2011

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

DPA Resistant AES on FPGA Using Partial DDL.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009
Lightweight Cryptography for FPGAs.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Compact FPGA implementation of Camellia.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Chai-Tea, Cryptographic Hardware Implementations of xTEA.
Proceedings of the Progress in Cryptology, 2008

2007
Cryptography on a Speck of Dust.
Computer, 2007

2006
Energy Comparison of AES and SHA-1 for Ubiquitous Computing.
Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2006

2005
Energy Scalable Universal Hashing.
IEEE Trans. Computers, 2005

State of the Art in Ultra-Low Power Public Key Cryptography for Wireless Sensor Networks.
Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005

2004
Public Key Cryptography in Sensor Networks - Revisited.
Proceedings of the Security in Ad-hoc and Sensor Networks, First European Workshop, 2004

1999
DES auf FPGAs - Hochgeschwindigkeits-Architekturen für den Data Encryption Standard auf rekonfigurierbarer Hardware.
Datenschutz und Datensicherheit, 1999

1998
Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine.
Proceedings of the Selected Areas in Cryptography '98, 1998


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