Jessy Clédière
Orcid: 0000-0001-6239-8825
According to our database1,
Jessy Clédière
authored at least 26 papers
between 2005 and 2023.
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Bibliography
2023
Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2021
EM Fault Model Characterization on SoCs: From Different Architectures to the Same Fault Model.
Proceedings of the 18th Workshop on Fault Detection and Tolerance in Cryptography, 2021
Proceedings of the Smart Card Research and Advanced Applications, 2021
2019
Proceedings of the Information Security Theory and Practice, 2019
2017
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017
2015
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015
From Code Review to Fault Injection Attacks: Filling the Gap Using Fault Model Inference.
Proceedings of the Smart Card Research and Advanced Applications, 2015
2014
Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor.
J. Electron. Test., 2013
Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2011
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.
J. Cryptol., 2011
Proceedings of the HOST 2011, 2011
2010
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.
Proceedings of the 15th European Test Symposium, 2010
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
2008
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 2008 ACM Symposium on Information, Computer and Communications Security, 2008
2007
IEEE Trans. Inf. Forensics Secur., 2007
IACR Cryptol. ePrint Arch., 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
2005
IACR Cryptol. ePrint Arch., 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005