Jesús Ruiz-Amaya

According to our database1, Jesús Ruiz-Amaya authored at least 16 papers between 2004 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A Low Noise Amplifier for Neural Spike Recording Interfaces.
Sensors, 2015

2012
A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression.
IEEE Trans. Biomed. Circuits Syst., 2012

Behavioral modeling of pipeline ADC building blocks.
Int. J. Circuit Theory Appl., 2012

2011
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A power efficient neural spike recording channel with data bandwidth reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
An ultra-low power consumption 1-V, 10-bit succesive approximation ADC.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Electrical-level synthesis of pipeline ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A 12-bit CMOS Current Steering D/A Converter for Embedded Systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Behavioral modeling simulation and high-level synthesis of pipeline A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators.
Proceedings of the 2004 Design, 2004


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