Jiang Chau Wang
Orcid: 0000-0002-3960-4026Affiliations:
- University of Sao Paulo, Brazil
According to our database1,
Jiang Chau Wang
authored at least 54 papers
between 1995 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on scopus.com
-
on orcid.org
On csauthors.net:
Bibliography
2021
Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
2019
Exploring Tabu search based algorithms for mapping and placement in NoC-based reconfigurable systems.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Mapping and Placement in NoC-based Reconfigurable Systems Using an Adaptive Tabu Search Algorithm.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
2016
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2016
2015
Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems.
Int. J. Reconfigurable Comput., 2015
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models.
J. Electron. Test., 2015
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS.
Proceedings of the 16th Latin-American Test Symposium, 2015
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs.
Proceedings of the 15th Latin American Test Workshop, 2014
2013
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification.
J. Electron. Test., 2013
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions.
Proceedings of the 8th International Design and Test Symposium, 2013
3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013
2012
Int. J. Reconfigurable Comput., 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012
2011
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling.
J. Electron. Test., 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
2010
Trans. Comput. Sci., 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training.
Proceedings of the International Joint Conference on Neural Networks, 2009
2007
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2005
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
2004
J. Electron. Test., 2004
2003
Microelectron. Reliab., 2003
2002
BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units.
Proceedings of the 3rd Latin American Test Workshop, 2002
A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications.
Proceedings of the 3rd Latin American Test Workshop, 2002
2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Self Test Built-in Plan for Data-Path Functional Units.
Proceedings of the 1st Latin American Test Workshop, 2000
1999
Architectural Transformations for Hierarchical Algorithmic Descriptions.
Proceedings of the VLSI: Systems on a Chip, 1999
1998
Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1995
Collective Test Generation and Test Set Compaction.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995