Marius Strum

According to our database1, Marius Strum authored at least 50 papers between 1998 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems.
Int. J. Reconfigurable Comput., 2015

A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models.
J. Electron. Test., 2015

NoC-Based Protection for SoC Time-Driven Attacks.
IEEE Embed. Syst. Lett., 2015

Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS.
Proceedings of the 16th Latin-American Test Symposium, 2015

TSV protection: Towards secure 3D-MPSoC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014
3D-LeukoNoC: A dynamic NoC protection.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs.
Proceedings of the 15th Latin American Test Workshop, 2014

Elastic security zones for NoC-based 3D-MPSoCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification.
J. Electron. Test., 2013

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

PrOCov: Probabilistic output coverage model.
Proceedings of the 14th Latin American Test Workshop, 2013

Formal equivalence checking between high-level and RTL hardware designs.
Proceedings of the 14th Latin American Test Workshop, 2013

QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Long range dependence in intrachip transaction level traffic.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A strategy for mapping reconfigurable cores in NoCs.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions.
Proceedings of the 8th International Design and Test Symposium, 2013

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013

Scalable NoC-based architecture of neural coding for new efficient associative memories.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection.
Int. J. Reconfigurable Comput., 2012

Workload and task characterization based on operation modes timing analysis.
Proceedings of the IEEE 25th International SOC Conference, 2012

Hybrid-on-chip communication architecture for dynamic MP-SoC protection.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

2011
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling.
J. Electron. Test., 2011

Dynamic NoC-based architecture for MPSoC security implementation.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Formally verifying an RTOS scheduling monitor IP core in embedded systems.
Proceedings of the 12th Latin American Test Workshop, 2011

2010
Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection.
Trans. Comput. Sci., 2010

The LRD traffic impact on the NoC-based SoCs.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Automatic generation of a parameter-domain-based functional input coverage model.
Proceedings of the 11th Latin American Test Workshop, 2010

2009
A PD-based methodology to enhance efficiency in testbenches with random stimulation.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training.
Proceedings of the International Joint Conference on Neural Networks, 2009

2008
Burst-Mode Asynchronous Controllers on FPGA.
Int. J. Reconfigurable Comput., 2008

2007
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2005
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

A Dynamically Reconfigurable Bluetooth Base Band Unit.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.
J. Electron. Test., 2004

2003
Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems.
Microelectron. Reliab., 2003

Exploring Models of Computation through Static Analysis.
Proceedings of the Forum on specification and Design Languages, 2003

2002
Power Management Exploration for a Block Turbo Decoder.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units.
Proceedings of the 3rd Latin American Test Workshop, 2002

A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications.
Proceedings of the 3rd Latin American Test Workshop, 2002

2001
Synthesis of Multi-Burst Controllers as Modified Huffman Machines.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Self Test Built-in Plan for Data-Path Functional Units.
Proceedings of the 1st Latin American Test Workshop, 2000

1999
Architectural Transformations for Hierarchical Algorithmic Descriptions.
Proceedings of the VLSI: Systems on a Chip, 1999

SINMEF - A Decomposition Based Synthesis Tool for Large FSMs.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

A Methodology for Minimum Area Cellular Automata Generation.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


  Loading...