Jianyi Yu
Orcid: 0009-0005-5267-3340
According to our database1,
Jianyi Yu authored at least 7 papers
between 2021 and 2025.
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Bibliography
2025
AM-CIM: Approximate Memory Based Near Sensor Compute-in-Memory Architecture for Keyword Spotting.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025
A Digital SRAM-Based Compute-In-Memory Macro for Weight-Stationary Dynamic Matrix Multiplication in Transformer Attention Score Computation.
CoRR, November, 2025
2023
An Edge Neuromorphic Hardware With Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
2022
A Lightweight Spiking GAN Model for Memristor-centric Silicon Circuit with On-chip Reinforcement Adversarial Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
TEDOP: A Tiny Event-Driven Neural Network Hardware Core Enabling On-Chip Spike-Driven Synaptic Plasticity.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A Heterogeneous Spiking Neural Network for Computationally Efficient Face Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021