Xiaotao Jia

According to our database, Xiaotao Jia authored at least 19 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.

Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

2023

IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations.

Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.

Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao

Sci. China Inf. Sci., April, 2023

2022

Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.

Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao

IEEE Trans. Computers, 2022

2021

Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.

Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao

IEEE Trans. Neural Networks Learn. Syst., 2021

2020

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing.

Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao

ACM J. Emerg. Technol. Comput. Syst., 2020

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.

Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao

CCF Trans. High Perform. Comput., 2020

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique.

Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.

Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.

Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Electromigration Design Rule aware Global and Detailed Routing Algorithm.

Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Spintronics based stochastic computing for efficient Bayesian inference system.

Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2016

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.

Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.

Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

A New Random-Walk Based Label Propagation Community Detection Algorithm.

Chang Su, Xiaotao Jia, Xianzhong Xie, Yue Yu

Proceedings of the IEEE/WIC/ACM International Conference on Web Intelligence and Intelligent Agent Technology, 2015

2014

MCFRoute: a detailed router based on multi-commodity flow method.

Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014