Jiayi Huang

Orcid: 0000-0003-4011-6668

Affiliations:
  • University of California Santa Barbara, Department of Electrical and Computer Engineering, CA, USA
  • Texas A&M University, College Station, TX, USA (PhD 2020)


According to our database1, Jiayi Huang authored at least 20 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
WHISTLE: CPU Abstractions for Hardware and Software Memory Safety Invariants.
IEEE Trans. Computers, March, 2023

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022
Toward Taming the Overhead Monster for Data-flow Integrity.
ACM Trans. Design Autom. Electr. Syst., 2022

RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity.
IEEE Trans. Computers, 2022

MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures.
IEEE Comput. Archit. Lett., 2022

PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Remote Control: A Simple Deadlock Avoidance Scheme for Modular Systems-on-Chip.
IEEE Trans. Computers, 2021

Computing En-Route for Near-Data Processing.
IEEE Trans. Computers, 2021

A Voting Approach for Adaptive Network-on-Chip Power-Gating.
IEEE Trans. Computers, 2021

Attacks of the Knights: Exploiting Non Uniform Cache Access Time.
CoRR, 2021

Continual Learning Approach for Improving the Data and Computation Mapping in Near-Memory Processing System.
CoRR, 2021

Communication Algorithm-Architecture Co-Design for Distributed Deep Learning.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
ReViCe: Reusing Victim Cache to Prevent Speculative Cache Leakage.
Proceedings of the IEEE Secure Development, SecDev 2020, Atlanta, GA, USA, 2020

2019
Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip.
CoRR, 2019

Coloring Big Graphs with AlphaGoZero.
CoRR, 2019

Active-Routing: Compute on the Way for Near-Data Processing.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2017
APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Packet coalescing exploiting data redundancy in GPGPU architectures.
Proceedings of the International Conference on Supercomputing, 2017

2016
POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism For Energy-Efficient Networks-on-Chip.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016


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