Jie Li

According to our database, Jie Li authored at least 17 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs.

Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets.

Hongchen Li, Liyi Xiao, Chunhua Qi, Jie Li

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).

Jie Li, Pedro Reviriego, Shanshan Liu, Liyi Xiao, Fabrizio Lombardi

Integr., 2021

2020

An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA.

Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Linzhe Li

IEEE Trans. Reliab., 2020

Scheme for periodical concurrent fault detection in parallel CRC circuits.

Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi

IET Comput. Digit. Tech., 2020

2019

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).

Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs.

Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Tianqi Wang

Proceedings of the International Conference on IC Design and Technology, 2019

A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network.

Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.

Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.

Hongchen Li, Liyi Xiao, Jie Li, He Liu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.

Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li

IEEE Trans. Very Large Scale Integr. Syst., 2018

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs.

Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Chunhua Qi, Jiaqiang Li, Mingjiang Wang

Microelectron. Reliab., 2018

Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.

Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

Low redundancy matrix-based codes for adjacent error correction with parity sharing.

Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A fast and accurate fault injection platform for SRAM-based FPGAs.

Rongsheng Zhang, Liyi Xiao, Jie Li

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A method to estimate cross-section of circuits at RTL levels.

Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.

Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015