Liyi Xiao
Orcid: 0000-0003-1486-6377
According to our database1,
Liyi Xiao
authored at least 76 papers
between 2001 and 2023.
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Bibliography
2023
A Compact RF Energy Harvesting Wireless Sensor Node with an Energy Intensity Adaptive Management Algorithm.
Sensors, October, 2023
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits.
IEEE Access, 2022
IEEE Access, 2022
2021
Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes.
IEEE Trans. Emerg. Top. Comput., 2021
Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).
Integr., 2021
Sci. China Inf. Sci., 2021
2020
An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA.
IEEE Trans. Reliab., 2020
Knowl. Based Syst., 2020
Inf. Sci., 2020
IET Comput. Digit. Tech., 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
CoRR, 2019
CoRR, 2019
Single-event upset prediction in static random access memory cell account for parameter variations.
Sci. China Inf. Sci., 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019
Proceedings of the International Conference on IC Design and Technology, 2019
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Microelectron. Reliab., 2018
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.
Microelectron. Reliab., 2018
Knowl. Based Syst., 2018
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th International Conference on Pattern Recognition, 2018
2017
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Reliab., 2017
A method to recover critical bits under a double error in SEC-DED protected memories.
Microelectron. Reliab., 2017
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).
Microelectron. Reliab., 2017
A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Extend orthogonal Latin square codes for 32-bit data protection in memory applications.
Microelectron. Reliab., 2016
2015
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.
IEEE Trans. Reliab., 2015
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology.
Microelectron. Reliab., 2015
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Novel technique for P-hit single-event transient mitigation using enhance dummy transistor.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation.
Microelectron. J., 2014
Circuits Syst. Signal Process., 2014
2013
IEEE Micro, 2013
A Low Power Built-in Self-Test Scheme Based on Overlapping Bit Swapping Linear Feedback Shift Register.
J. Low Power Electron., 2013
2012
J. Low Power Electron., 2012
2011
Microelectron. J., 2011
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping.
J. Electron. Test., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
2010
DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2009
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.
Proceedings of the 46th Design Automation Conference, 2009
2008
Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
J. Comput. Sci. Technol., 2002
2001
Proceedings of the Proceedings 34th Annual Simulation Symposium (SS 2001), 2001