Costas Argyrides

According to our database1, Costas Argyrides authored at least 34 papers between 2007 and 2023.

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Bibliography

2023
Utilizing ECC Analytics to Improve Memory Lifecycle Management.
Proceedings of the IEEE International Test Conference, 2023

2022
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

A Novel Protection Technique for Embedded Memories with Optimized PPA.
Proceedings of the IEEE International Test Conference, 2022

2019
Efficient Concurrent Error Detection for SEC-DAEC Encoders.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2018

2013
Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors.
IEEE Trans. Reliab., 2013

2012
Efficient error detection in Double Error Correction BCH codes for memory applications.
Microelectron. Reliab., 2012

2011
Matrix Codes for Reliable and Cost Efficient Memory Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.
IEEE Trans. Reliab., 2011

Fault Tolerant Single Error Correction Encoders.
J. Electron. Test., 2011

Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Evaluation of a new low cost software level fault tolerance technique to cope with soft errors.
Proceedings of the 11th Latin American Test Workshop, 2010

Improved Yield in Nanotechnology Circuits Using Non-square Meshes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Improving reliability for bit parallel finite field multipliers using Decimal Hamming.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Multiple Bit Error Detection and Correction in Memory.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Reliability aware yield improvement technique for nanotechnology based circuits.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Single element correction in sorting algorithms with minimum delay overhead.
Proceedings of the 10th Latin American Test Workshop, 2009

Increasing memory yield in future technologies through innovative design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A fast error correction technique for matrix multiplication algorithms.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Single Error Correcting Finite Field Multipliers Over GF(2m).
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Area Reliability Trade-Off in Improved Reed Muller Coding.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Multiple Event Upsets Aware FPGAs Using Protected Schemes.
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008

Yield improvement and power aware low cost memory chips.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Improved decoding algorithm for high reliable reed muller coding.
Proceedings of the 2007 IEEE International SOC Conference, 2007

High defect tolerant low cost memory chips.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A soft error robust and power aware memory design.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Multiple Upsets Tolerance in SRAM Memory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Highly Reliable Power Aware Memory Design.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007


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