Jien-Chung Lo
  According to our database1,
  Jien-Chung Lo
  authored at least 49 papers
  between 1988 and 2006.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2006
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).
    
  
    IEEE Trans. Computers, 2006
    
  
    Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
    
  
    Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
    
  
  2005
On-chip short-time interval measurement system for high-speed signal timing characterization.
    
  
    J. Syst. Archit., 2005
    
  
    Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
    
  
  2004
    J. Electron. Test., 2004
    
  
    Proceedings of the 9th European Test Symposium, 2004
    
  
  2003
    IEEE Trans. Instrum. Meas., 2003
    
  
    Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
    
  
On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization.
    
  
    Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
    
  
  2002
    IEEE Trans. Computers, 2002
    
  
    Proceedings of the High Performance Computing, 2002
    
  
    Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
    
  
  2001
    IEEE Des. Test Comput., 2001
    
  
    Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
    
  
  2000
    J. Electron. Test., 2000
    
  
    Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
    
  
  1999
    Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
    
  
  1998
Correction to "A Fast Binary Adder with Conditional Carry Generation" IEEE Transaction on Computers 46(2) 248-253 (1997).
    
  
    IEEE Trans. Computers, 1998
    
  
    Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
    
  
    Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
    
  
  1997
    Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
    
  
  1996
    IEEE Trans. Computers, 1996
    
  
    IEEE Trans. Computers, 1996
    
  
Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library.
    
  
    Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
    
  
    Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
    
  
  1995
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations.
    
  
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
    
  
    Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
    
  
  1994
    IEEE J. Solid State Circuits, May, 1994
    
  
    IEEE Trans. Computers, 1994
    
  
  1993
    IEEE J. Solid State Circuits, February, 1993
    
  
    IEEE J. Solid State Circuits, January, 1993
    
  
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning.
    
  
    IEEE Trans. Computers, 1993
    
  
    Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
    
  
A Probabilistic Measurement for Totally Self-Checking Circuits.
  
    Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
    
  
  1992
An SFS Berger check prediction ALU and its application to self-checking processor designs.
    
  
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
    
  
    Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
    
  
    Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
    
  
    Proceedings of the Digest of Papers: FTCS-22, 1992
    
  
  1991
    Proceedings of the 16th Conference on Local Computer Networks, 1991
    
  
  1990
    IEEE Trans. Computers, 1990
    
  
  1989
    Proceedings of the 9th Symposium on Computer Arithmetic, 1989
    
  
  1988
The design of fast totally self-checking Berger code checkers based on Berger code partitioning.
    
  
    Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988