Jin Sha

Orcid: 0000-0002-0266-3583

Affiliations:
  • Nanjing University, School of Electronic Science and Engineering, China
  • Stanford University, CA, USA (2012-2013)
  • Nanjing University, China (PhD 2007)


According to our database1, Jin Sha authored at least 67 papers between 2006 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Electro-Optical Reed-Muller Code Decoders Based on Integrated Optics.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2026

An Error Correction Technique for Product Codes Construction of PAC Codes.
IEEE Trans. Green Commun. Netw., 2026

Robust Cross-Domain Drone RFFI Method Using Domain-Invariant Adversarial Learning and Manifold Regularization.
IEEE Trans. Cogn. Commun. Netw., 2026

2025
Receiver-Agnostic Radio Frequency Fingerprinting via Domain-Invariant Feature Learning.
IEEE Commun. Lett., October, 2025

Channel-Resilient and Low-Power Radio Frequency Fingerprint Identification for VDES-SAT.
IEEE Trans. Cogn. Commun. Netw., August, 2025

A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline.
ACM Trans. Design Autom. Electr. Syst., July, 2025

An Energy-Efficient FPGA Accelerator for Swin Transformer.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

Physical Layer Authentication via Conditional Variational Auto-Encoder for AIS.
IEEE Trans. Green Commun. Netw., June, 2025

Radio Frequency Fingerprint Identification Using Conditional Generative Adversarial Network for SAT-AIS.
IEEE Trans. Aerosp. Electron. Syst., February, 2025

Toward Robust Radio Frequency Fingerprint Identification via Adaptive Semantic Augmentation.
IEEE Trans. Inf. Forensics Secur., 2025

2024
RF Fingerprinting Identification in Low SNR Scenarios for Automatic Identification System.
IEEE Trans. Wirel. Commun., March, 2024

Radio Frequency Fingerprint Identification Based on Variational Autoencoder for GNSS.
IEEE Geosci. Remote. Sens. Lett., 2024

Toward Intelligent Lightweight and Efficient UAV Identification With RF Fingerprinting.
IEEE Internet Things J., 2024

Efficient UAV Identification Leveraging Multi-Resolution Analysis and Multi-Scale ResNet.
Proceedings of the 99th IEEE Vehicular Technology Conference, 2024

2023
1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

The Use of SNN for Ultralow-Power RF Fingerprinting Identification With Attention Mechanisms in VDES-SAT.
IEEE Internet Things J., September, 2023

An Improved Critical Set for List Decoding of Polar Codes.
IEEE Commun. Lett., September, 2023

An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes.
IEEE Commun. Lett., April, 2023

RF Fingerprinting Identification Based on Spiking Neural Network for LEO-MIMO Systems.
IEEE Wirel. Commun. Lett., 2023

2021
Efficient HLS Implementation of Fast Linear Discriminant Analysis Classifier.
IEEE Embed. Syst. Lett., 2021

2019
Efficient Channel Estimator With Angle-Division Multiple Access.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Joint Detection and Decoding of Polar-Coded OFDM-IDMA Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Stage-Combined Belief Propagation Decoder for Polar Codes.
J. Signal Process. Syst., 2018

Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A low complexity LDPC-BCH concatenated decoder for NAND flash memory.
IEICE Electron. Express, 2018

4.7-Gb/s LDPC Decoder on GPU.
IEEE Commun. Lett., 2018

Polar-Coded Forward Error Correction for MLC NAND Flash Memory Polar FEC for NAND Flash Memory.
CoRR, 2018

Polar-coded forward error correction for MLC NAND flash memory.
Sci. China Inf. Sci., 2018

2017
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Optimized sorting network for successive cancellation list decoding of polar codes.
IEICE Electron. Express, 2017

An access pattern based adaptive mapping function for GPGPU scratchpad memory.
IEICE Electron. Express, 2017

The VLSI architecture for channel estimation based on ADMA.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Joint detection and decoding for polar-coded OFDM-IDMA systems.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Joint detection and decoding for non-binary LDPC coded MIMO systems.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices.
Sensors, 2016

An Efficient FPGA Implementation for 2-D MUSIC Algorithm.
Circuits Syst. Signal Process., 2016

Beyond 100Gbps Encoder Design for Staircase Codes.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Stage-combined belief propagation decoding of polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A high throughput belief propagation decoder architecture for polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Performance Comparison of Cross-Like Hall Plates with Different Covering Layers.
Sensors, 2015

A stage-reduced low-latency successive cancellation decoder for polar codes.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2014
A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Efficient symbol reliability based decoding for QCNB-LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Hardware architecture for list successive cancellation polar decoder.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Memory efficient EMS decoding for non-binary LDPC codes.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Efficient EMS decoding for non-binary LDPC codes.
Proceedings of the International SoC Design Conference, 2012

Efficient network for non-binary QC-LDPC decoder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Memory efficient column-layered decoder design for non-binary LDPC codes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Efficient Reed-Solomon based LDPC decoders.
Proceedings of the International SoC Design Conference, 2011

Memory efficient decoder design of nonbinary LDPC codes.
Proceedings of the International SoC Design Conference, 2011

2010
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An Efficient VLSI Architecture for Nonbinary LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Layered decoding for non-binary LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low power decoder design for QC-LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Multi-Gb/s LDPC Code Design and Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An improved scaled DCT architecture.
IEEE Trans. Consumer Electron., 2009

LDPC decoder design for high rate wireless personal area networks.
IEEE Trans. Consumer Electron., 2009

Area-efficient reed-solomon decoder design for optical communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Decoder Design for RS-Based LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

An improved min-sum based column-layered decoding algorithm for LDPC codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

LDPC Decoder Design for IEEE 802.15 Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2006
An FPGA Implementation of Array LDPC Decoder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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