Yuxiang Fu

Orcid: 0000-0003-1351-5460

According to our database¹, Yuxiang Fu authored at least 49 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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On csauthors.net:

Bibliography

2024

HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data.

[BibT_eX]

[DOI]

IEEE Access, 2024

2023

A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow.

[BibT_eX]

[DOI]

IEEE Des. Test, December, 2023

A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks.

[BibT_eX]

[DOI]

Qinyu Chen

Chang Gao

Yuxiang Fu

IEEE Trans. Very Large Scale Integr. Syst., 2022

Hap-pulse: A Wearable Vibrotactile Glove for Medical Pulse Wave Rendering.

[BibT_eX]

[DOI]

IEEE Trans. Haptics, 2022

A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Huicore: A Generalized Hardware Accelerator for Complicated Functions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Improving the thermal reliability of photonic chiplets on multicore processors.

[BibT_eX]

[DOI]

Integr., 2022

Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Unsupervised Learning Based on Temporal Coding Using STDP in Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

PHANES: ReRAM-based photonic accelerator for deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2022

Deep Spiking Neural Network with Ternary Spikes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021

Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Symmetric-Mapping LUT-Based Method and Architecture for Computing X<sup>Y</sup>-Like Functions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Stochastic Geometry Analysis of Wireless Backhaul Networks with Beamforming in Roadside Environments.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2021

Adaptive Multi-Task Human-Robot Interaction Based on Human Behavioral Intention.

[BibT_eX]

[DOI]

IEEE Access, 2021

<sup>2</sup>β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

An Efficient Software List Sphere Decoder for Polar Codes.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Joint Detection and Decoding of Polar-Coded OFDM-IDMA Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Optimal Primary Exclusive Region Design for Cognitive Radio VANETs on Multiple Roads.

[BibT_eX]

[DOI]

Proceedings of the 88th IEEE Vehicular Technology Conference, 2018

2017

Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Optimized sorting network for successive cancellation list decoding of polar codes.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2016

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Exploring stacked main memory architecture for 3D GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Yuxiang Fu

Timeline

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On csauthors.net:

Bibliography

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