Weifeng He
Orcid: 0000-0002-7753-644X
According to our database1,
Weifeng He
authored at least 93 papers
between 2005 and 2024.
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Bibliography
2024
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, February, 2024
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core.
IEEE J. Solid State Circuits, February, 2024
A novel physically interpretable end-to-end network for stress monitoring in laser shock peening.
Comput. Ind., February, 2024
2023
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Surface stress monitoring of laser shock peening using AE time-scale texture image and multi-scale blueprint separable convolutional networks with attention mechanism.
Expert Syst. Appl., August, 2023
PointCNT: A One-Stage Point Cloud Registration Approach Based on Complex Network Theory.
Remote. Sens., July, 2023
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A Novel Approach for Surface Integrity Monitoring in High-Energy Nanosecond-Pulse Laser Shock Peening: Acoustic Emission and Hybrid-Attention CNN.
IEEE Trans. Ind. Informatics, March, 2023
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
Online Evaluation of Surface Hardness for Aluminum Alloy in LSP Using Modal Acoustic Emission.
IEEE Trans. Instrum. Meas., 2022
MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification.
IEEE Trans. Geosci. Remote. Sens., 2022
Hierarchical photoelectric hybrid packet switching network for high-performance computing.
JOCN, 2022
All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing.
IEEE Trans. Very Large Scale Integr. Syst., 2021
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the IEEE International Conference on Signal Processing, 2021
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Dual-rail Based Dynamic Voltage and Frequency Scaling for Wide-Voltage-Range Processor.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.
Microelectron. J., 2017
IEEE J. Solid State Circuits, 2017
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.
Integr., 2017
Integr., 2017
A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.
J. Circuits Syst. Comput., 2016
High performance parallel turbo decoder with configurable interleaving network for LTE application.
Integr., 2016
IEICE Electron. Express, 2016
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Electron. Express, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
An automatic translation and parallelization system for general purpose reconfigurable processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEICE Electron. Express, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard.
IEICE Electron. Express, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the Eighth International Conference on Signal Image Technology and Internet Based Systems, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Integr., 2010
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2005
Efficient frame-level pipelined array architecture for full-search block-matching motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005