Weifeng He

According to our database1, Weifeng He authored at least 50 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. on Circuits and Systems, 2019

2018
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.
IEEE Trans. VLSI Syst., 2017

Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.
Microelectronics Journal, 2017

Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques.
J. Solid-State Circuits, 2017

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.
Integration, 2017

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras.
Integration, 2017

A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A static-placement, dynamic-issue framework for CGRA loop accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.
Journal of Circuits, Systems, and Computers, 2016

High performance parallel turbo decoder with configurable interleaving network for LTE application.
Integration, 2016

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding.
IEICE Electronic Express, 2016

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.
IEEE Trans. on Circuits and Systems, 2015

Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems.
IEICE Transactions, 2015

Design optimization for capacitive-resistively driven on-chip global interconnect.
IEICE Electronic Express, 2015

Resource-saving compile flow for coarse-grained reconfigurable architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Improved pipeline data flow for DySER-based platform.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

An automatic translation and parallelization system for general purpose reconfigurable processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Improved Max-Log-MAP BICM-IDD receiver for MIMO systems.
IEICE Electronic Express, 2014

Area and throughput efficient IDCT/IDST architecture for HEVC standard.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard.
IEICE Electronic Express, 2013

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst., 2012

Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC.
Proceedings of the Eighth International Conference on Signal Image Technology and Internet Based Systems, 2012

Contention and energy aware mapping for real-time applications on Network-on-Chip.
Proceedings of the International SoC Design Conference, 2012

A pre-emphasis circuit design for high speed on-chip global interconnect.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
A general statistical estimation for application mapping in Network-on-Chip.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Robust design of sub-threshold flip-flop cells for wireless sensor network.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A clock-less transceiver for global interconnect.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Mitigating FPGA interconnect soft errors by in-place LUT inversion.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Automatic compilation flow for a coarse-grained reconfigurable processor.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Statistical estimation and evaluation for communication mapping in Network-on-Chip.
Integration, 2010

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

An efficient VLSI architecture for extended variable block sizes motion estimation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2007
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Efficient frame-level pipelined array architecture for full-search block-matching motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


  Loading...