# Jooheung Lee

According to our database

Collaborative distances:

^{1}, Jooheung Lee authored at least 26 papers between 2004 and 2017.Collaborative distances:

## Timeline

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## Bibliography

2017

Write-Amount-Aware Management Policies for STT-RAM Caches.

IEEE Trans. VLSI Syst., 2017

Energy efficient processing of motion estimation for embedded multimedia systems.

Multimedia Tools Appl., 2017

Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC.

Intelligent Automation & Soft Computing, 2017

2016

Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences.

J. Sensors, 2016

2015

Activity-Based Resource Allocation for Motion Estimation Engines.

Journal of Circuits, Systems, and Computers, 2015

2014

Self-Adapting Resource Escalation for Resilient Signal Processing Architectures.

Signal Processing Systems, 2014

2013

Fault Demotion Using Reconfigurable Slack (FaDReS).

IEEE Trans. VLSI Syst., 2013

2012

A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration.

Signal Processing Systems, 2012

Error surface-aware modeling algorithm for quarter-pixel motion estimation.

IEEE Trans. Consumer Electronics, 2012

2011

Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation.

Embedded Systems Letters, 2011

2010

A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration.

Proceedings of the IEEE International Conference on Acoustics, 2010

Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors.

Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009

Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration.

ACM Trans. Embedded Comput. Syst., 2009

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching.

IEEE Trans. Circuits Syst. Video Techn., 2009

Efficient VLSI architecture for video transcoding.

IEEE Trans. Consumer Electronics, 2009

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration.

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008

Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study.

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field.

Proceedings of the 2008 International Conference on Security & Management, 2008

2006

Block-based frequency scalable technique for efficient hierarchical coding.

IEEE Trans. Signal Processing, 2006

An efficient architecture for motion estimation and compensation in the transform domain.

IEEE Trans. Circuits Syst. Video Techn., 2006

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.

IEEE Trans. Circuits Syst. Video Techn., 2006

2005

High Performance Array Processor for Video Decoding.

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004

An Architecture for Motion Estimation in the Transform Domain.

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Efficient VLSI implementation of inverse discrete cosine transform [image coding applications].

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004