José-María Arnau
Orcid: 0000-0002-0336-9191Affiliations:
- Polytechnic University of Catalonia, ARCO, Barcelona, Spain (PhD 2015)
According to our database1,
José-María Arnau
authored at least 44 papers
between 2012 and 2023.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2023
J. Parallel Distributed Comput., April, 2023
ACM Trans. Embed. Comput. Syst., March, 2023
Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads.
J. Supercomput., 2023
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.
CoRR, 2023
δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions.
IEEE Trans. Computers, 2022
ACM Trans. Archit. Code Optim., 2022
CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs.
J. Syst. Archit., 2022
J. Syst. Archit., 2022
CoRR, 2022
2021
CoRR, 2021
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021
2020
IEEE Trans. Computers, 2020
ACM Trans. Archit. Code Optim., 2020
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
Proceedings of the 27th IEEE International Conference on High Performance Computing, 2020
2019
IEEE Trans. Computers, 2019
IEEE Micro, 2019
LSTM-Sharp: An Adaptable, Energy-Efficient Hardware Accelerator for Long Short-Term Memory.
CoRR, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator.
IEEE Micro, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
2015
2014
Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
2013
TEAPOT: a toolset for evaluating performance, power and image quality on mobile graphics systems.
Proceedings of the International Conference on Supercomputing, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012