Wim Heirman

According to our database1, Wim Heirman authored at least 40 papers between 2005 and 2018.

Collaborative distances :
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2018
Multi-Stage CPI Stacks.
Computer Architecture Letters, 2018

Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2017
Shared resource aware scheduling on power-constrained tiled many-core processors.
J. Parallel Distrib. Comput., 2017

2016
Boosting the Priority of Garbage: Scheduling Collection on Heterogeneous Multicore Processors.
TACO, 2016

Shared resource aware scheduling on power-constrained tiled many-core processors.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization.
Computer Architecture Letters, 2015

The load slice core microarchitecture.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Chrysso: an integrated power manager for constrained many-core processors.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
An Evaluation of High-Level Mechanistic Core Models.
TACO, 2014

BarrierPoint: Sampled simulation of multi-threaded applications.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor.
Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, 2014

Undersubscribed threading on clustered cache architectures.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Cooperative cache scrubbing.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling.
TACO, 2013

Node Performance and Energy Analysis with the Sniper Multi-core Simulator.
Proceedings of the Tools for High Performance Computing 2013, 2013

Making Communication a First-Class Citizen in Multicore Partitioning.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

Sampled simulation of multi-threaded applications.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Fairness-aware scheduling on single-ISA heterogeneous multi-cores.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
The Impact of Global Communication Latency at Extreme Scales on Krylov Methods.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Power-aware multi-core simulation for early design stage hardware/software co-optimization.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Dynamic data folding with parameterizable FPGA configurations.
ACM Trans. Design Autom. Electr. Syst., 2011

Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation.
Proceedings of the Conference on High Performance Computing Networking, 2011

RecoNoC: A reconfigurable network-on-chip.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

2010
Performance evaluation for passive-type Optical network-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

PinComm: Characterizing Intra-application Communication for the Many-Core Era.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

2009
Efficient memory management for hardware accelerated Java Virtual Machines.
ACM Trans. Design Autom. Electr. Syst., 2009

Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects.
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

Strategies for dynamic memory allocation in hybrid architectures.
Proceedings of the 6th Conference on Computing Frontiers, 2009

2008
Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems.
Photonic Network Communications, 2008

Rent's rule and parallel programs: characterizing network traffic behavior.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Efficient measurement of data flow enabling communication-aware parallelisation.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

2007
Predicting reconfigurable interconnect performance in distributed shared-memory systems.
Integration, 2007

Synthetic traffic generation as a tool for dynamic interconnect evaluation.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

2006
Congestion modeling for reconfigurable inter-processor networks.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

2005
Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005


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