Joren Dumoulin

Orcid: 0009-0005-0692-1227

According to our database1, Joren Dumoulin authored at least 9 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
FlexiGen: An Automated AI Accelerator Generation Framework With Decoupled-Access-Execute and Dynamic Dataflows.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026

Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026

A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.
CoRR, 2024

Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024


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