Vikram Jain

Orcid: 0000-0002-1267-1683

According to our database1, Vikram Jain authored at least 15 papers between 2019 and 2024.

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Bibliography

2024
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge.
IEEE J. Solid State Circuits, 2023

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge.
IEEE J. Solid State Circuits, 2023


PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Enabling real-time object detection on low cost FPGAs.
J. Real Time Image Process., 2022

CONVOLVE: Smart and seamless design of smart edge processors.
CoRR, 2022

TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators.
IEEE Trans. Computers, 2021

Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework.
CoRR, 2020

2019
Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019


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