José Carlos Alves

Orcid: 0000-0001-8728-9115

According to our database1, José Carlos Alves authored at least 20 papers between 1996 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Sensor Placement in an Irregular 3D Surface for Improving Localization Accuracy Using a Multi-Objective Memetic Algorithm.
Sensors, July, 2023

2021
A Novel Simulation Platform for Underwater Data Muling Communications Using Autonomous Underwater Vehicles.
Comput., 2021

2020
PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
An Alternative SNR Computation Method for ADC Testing.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem.
Microprocess. Microsystems, 2018

2015
An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2013
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A scalable array for Cellular Genetic Algorithms: TSP as case study.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2011
Experiment@Portugal.
Int. J. Eng. Pedagog., 2011

2010
Erlang Inspired Hardware.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
An FPGA-Based Embedded System for a Sailing Robot.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
A Custom Processor for a TDMA Solver in a CFD Application.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2005
A high-level tool for the design of custom image processing systems.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

A processor for testing mixed-signal cores in System-on-Chip.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

1999
FAFNER-Accelerating Nesting Problems with FPGAs.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Flexible hardware acceleration for nesting problems.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

RVC - A Reconfigurable Coprocessor for Vector Processing Applications.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A vector architecture for higher-order moments estimation.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996
ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order Moments.
Proceedings of the Vector and Parallel Processing, 1996


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