João Canas Ferreira
Orcid: 0000-0001-7471-3888
According to our database1,
João Canas Ferreira
authored at least 65 papers
between 1993 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2021
Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey.
ACM Comput. Surv., 2021
CoRR, 2021
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2021
2020
A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications.
J. Signal Process. Syst., 2020
IEEE/ACM Trans. Netw., 2020
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets.
IEEE Access, 2020
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing.
J. Signal Process. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem.
Microprocess. Microsystems, 2018
Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding.
J. Mobile Multimedia, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Scalable hardware architecture for disparity map computation and object location in real-time.
J. Real Time Image Process., 2016
Int. J. Circuit Theory Appl., 2016
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
ACM Trans. Reconfigurable Technol. Syst., 2015
A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks.
Microprocess. Microsystems, 2015
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014
A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
IEEE Trans. Ind. Informatics, 2013
Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011).
Microelectron. J., 2013
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.
Int. J. Reconfigurable Comput., 2013
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
2012
Microprocess. Microsystems, 2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the pHealth 2012, 2012
Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Analysis of error detection schemes: Toolchain support and hardware/software implications.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2008
Proceedings of the FPL 2008, 2008
2007
IET Comput. Digit. Tech., 2007
2006
J. Syst. Archit., 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware.
Proceedings of the Field Programmable Logic and Application, 2004
1999
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993