João Canas Ferreira

According to our database, João Canas Ferreira authored at least 65 papers between 1993 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A Binary Translation Framework for Automated Hardware Generation.

Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso

IEEE Micro, 2021

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey.

Nuno Paulino, João Canas Ferreira, João M. P. Cardoso

ACM Comput. Surv., 2021

A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA.

Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo

CoRR, 2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators.

Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira

Proceedings of the International Conference on Field-Programmable Technology, 2021

2020

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications.

Mário Lopes Ferreira, João Canas Ferreira

J. Signal Process. Syst., 2020

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems.

Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares, José Machado da Silva, Fernando J. Velez

IEEE/ACM Trans. Netw., 2020

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets.

Nuno Paulino, João Canas Ferreira, João M. P. Cardoso

IEEE Access, 2020

Parallel Implementation of K-Means Algorithm on FPGA.

Leonardo Alves Dias, João Canas Ferreira, Marcelo A. C. Fernandes

IEEE Access, 2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework.

Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Hardware architecture for integrate-and-fire signal reconstruction on FPGA.

Guilherme Carvalho, João Canas Ferreira, Vítor Grade Tavares

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing.

João Canas Ferreira, Francesca Palumbo

J. Signal Process. Syst., 2019

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem.

Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira

Microprocess. Microsystems, 2018

Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding.

Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares

J. Mobile Multimedia, 2018

Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator.

Mário Lopes Ferreira, João Canas Ferreira

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing.

Helder H. Avelar, João Canas Ferreira

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems.

Mário Lopes Ferreira, João Canas Ferreira, Michael Hübner

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

IEEE Trans. Very Large Scale Integr. Syst., 2017

MICPRO DSD 2015 special issue.

João Canas Ferreira, Paris Kitsos

Microprocess. Microsystems, 2017

Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices.

Joao Lopes, Diogo Sousa, João Canas Ferreira

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Towards a type 0 hypervisor for dynamic reconfigurable systems.

Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira, João Canas Ferreira

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator.

Miguel Carvalho, Mário Lopes Ferreira, João Canas Ferreira

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

Scalable hardware architecture for disparity map computation and object location in real-time.

Pedro Miguel Salgueiro dos Santos, João Canas Ferreira, José Silva Matos

J. Real Time Image Process., 2016

A small fully digital open-loop clock and data recovery circuit for wired BANs.

Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares

Int. J. Circuit Theory Appl., 2016

An FPGA implementation of a long short-term memory neural network.

João Canas Ferreira, Jose Fonseca

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Dynamically reconfigurable FFT processor for flexible OFDM baseband processing.

Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications.

Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira

Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

ACM Trans. Reconfigurable Technol. Syst., 2015

A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks.

Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares

Microprocess. Microsystems, 2015

Reconfigurable NC-OFDM Processor for 5G Communications.

Mário Lopes Ferreira, João Canas Ferreira

Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem.

Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Transparent acceleration of program execution using reconfigurable hardware.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Design and implementation of hybrid circuit/packet switching for wearable systems.

Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares

Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks.

Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems.

João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira

IEEE Trans. Ind. Informatics, 2013

Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011).

José Machado da Silva, Sylvie Renaud, João Canas Ferreira

Microelectron. J., 2013

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.

João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira

Int. J. Reconfigurable Comput., 2013

A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio.

Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques.

Filipe Sousa, Francis Anghinolfi, João Canas Ferreira

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Architecture for Transparent Binary Acceleration of Loops with Memory Accesses.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Run-time generation of partial FPGA configurations for subword operations.

Miguel Lino Silva, João Canas Ferreira

Microprocess. Microsystems, 2012

Run-time generation of partial FPGA configurations.

Miguel Lino Silva, João Canas Ferreira

J. Syst. Archit., 2012

A scalable array for Cellular Genetic Algorithms: TSP as case study.

Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A Wearable Sensor Network for Human Locomotion Data Capture.

Andreina Zambrano, Fardin Derogarian, Ruben Dias, Maria José Abreu, André P. Catarino, Ana Maria Rocha, José Machado da Silva, João Canas Ferreira, Vítor Grade Tavares, Miguel Velhote Correia

Proceedings of the pHealth 2012, 2012

Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks.

Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Analysis of error detection schemes: Toolchain support and hardware/software implications.

Ali Azarian, João Canas Ferreira, Stephan Werner, Zlatko Petrov, João M. P. Cardoso, Michael Hübner

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

From Instruction Traces to Specialized Reconfigurable Arrays.

João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010

Erlang Inspired Hardware.

Paulo Ferreira, João Canas Ferreira, José Carlos Alves

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Creation of Partial FPGA Configurations at Run-Time.

Miguel Lino Silva, João Canas Ferreira

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

FPGA-based rectification of stereo images.

João G. P. Rodrigues, João Canas Ferreira

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2008

Generation of partial FPGA configurations at run-time.

Miguel Lino Silva, João Canas Ferreira

Proceedings of the FPL 2008, 2008

2007

Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems.

Miguel Lino Silva, João Canas Ferreira

IET Comput. Digit. Tech., 2007

2006

Support for partial run-time reconfiguration of platform FPGAs.

Miguel Lino Silva, João Canas Ferreira

J. Syst. Archit., 2006

Exploiting dynamic reconfiguration of platform FPGAs: implementation issues.

Miguel L. Silva, João Canas Ferreira

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005

Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer.

João Canas Ferreira, Miguel M. Silva

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs.

Miguel Lino Silva, João Canas Ferreira

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

A Development Support System for Applications That Use Dynamically Reconfigurable Hardware.

João Canas Ferreira, José Silva Matos

Proceedings of the Field Programmable Logic and Application, 2004

1999

FAFNER-Accelerating Nesting Problems with FPGAs.

José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

Mixed hardware/software applications on dynamically reconfigurable hardware.

João Canas Ferreira, José Silva Matos

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Flexible hardware acceleration for nesting problems.

João Canas Ferreira, José Carlos Alves, Célio Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware.

João Canas Ferreira, José Silva Matos

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1994

Architecture of test support ICs for mixed-signal testing.

José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Approach to Testability Improvement of Mixed-Signal Boards.

José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Control and Observation of Analog Nodes in Mixed-Signal Boards.

José Silva Matos, Ana C. Leão, João Canas Ferreira

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993