Eishi Arima

According to our database, Eishi Arima authored at least 15 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

GreenCourier: Carbon-Aware Scheduling for Serverless Functions.

Mohak Chadha, Thandayuthapani Subramanian, Eishi Arima, Michael Gerndt, Martin Schulz, Osama Abboud

Proceedings of the 9th International Workshop on Serverless Computing, 2023

Probabilistic Job History Conversion and Performance Model Generation for Malleable Scheduling Simulations.

Isaías Comprés, Eishi Arima, Martin Schulz, Tiberiu Rotaru, Rui Machado

Proceedings of the High Performance Computing, 2023

Sustainability in HPC: Vision and Opportunities.

Mohak Chadha, Eishi Arima, Amir Raoofy, Michael Gerndt, Martin Schulz

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Hierarchical Resource Partitioning on Modern GPUs: A Reinforcement Learning Approach.

Urvij Saroliya, Eishi Arima, Dai Liu, Martin Schulz

Proceedings of the IEEE International Conference on Cluster Computing, 2023

2022

On the Convergence of Malleability and the HPC PowerStack: Exploiting Dynamism in Over-Provisioned and Power-Constrained HPC Systems.

Eishi Arima, Isaías Comprés, Martin Schulz

Proceedings of the High Performance Computing. ISC High Performance 2022 International Workshops - Hamburg, Germany, May 29, 2022

Optimizing Hardware Resource Partitioning and Job Allocations on Modern GPUs under Power Caps.

Eishi Arima, Minjoon Kang, Issa Saba, Josef Weidendorfer, Carsten Trinitis, Martin Schulz

Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

Orchestrated Co-scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning.

Issa Saba, Eishi Arima, Dai Liu, Martin Schulz

Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022

2021

Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip.

Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji, Mitsuhisa Sato

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

2020

Footprint-Aware Power Capping for Hybrid Memory Based Systems.

Eishi Arima, Toshihiro Hanawa, Carsten Trinitis, Martin Schulz

Proceedings of the High Performance Computing - 35th International Conference, 2020

Pattern-Aware Staging for Hybrid Memory Systems.

Eishi Arima, Martin Schulz

Proceedings of the High Performance Computing - 35th International Conference, 2020

Classification-Based Unified Cache Replacement via Partitioned Victim Address History.

Eishi Arima

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Evaluation of Power Management Control on the Supercomputer Fugaku.

Yuetsu Kodama, Tetsuya Odajima, Eishi Arima, Mitsuhisa Sato

Proceedings of the IEEE International Conference on Cluster Computing, 2020

2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.

Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the Design, Automation and Test in Europe, 2013