Thomas Wild

Wolfgang Schröder-Preikschat

Ulf Schlichtmann

ACM Trans. Design Autom. Electr. Syst., 2020

A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution.

[BibT_eX]

[DOI]

Proceedings of the 28th Euromicro International Conference on Parallel, 2020

HyVE: A Hybrid Voting-based Eviction Policy for Caches.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Industrial Engineering and Engineering Management, 2020

X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

APEC: improved acknowledgement prioritization through erasure coding in bufferless NoCs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

NEMESYS: near-memory graph copy enhanced system-software.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

Multicore Power Estimation using Independent Component Analysis Based Modeling.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

The information processing factory: a paradigm for life cycle management of dependable systems.

[BibT_eX]

[DOI]

Kenneth Michael Stewart

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

Network Coding in Networks-on-Chip with Lossy Links.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

Cryptographic Hashing in P4 Data Planes.

[BibT_eX]

[DOI]

Dominik Scholz

Andreas Oeldemann

Fabien Geyer

Sebastian Gallenmüller

Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018

Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS.

[BibT_eX]

[DOI]

Amir-Mohammad Rahmani

Proc. IEEE, 2018

Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models.

[BibT_eX]

[DOI]

Thomas Goldbrunner

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet.

[BibT_eX]

[DOI]

Andreas Oeldemann

Subramanian Shiva Shankar

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Design methodologies for enabling self-awareness in autonomous systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates.

[BibT_eX]

[DOI]

Pinxing Lin

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017

Efficient task spawning for shared memory and message passing in many-core architectures.

[BibT_eX]

[DOI]

Jürgen Teich

J. Syst. Archit., 2017

DiaSys: Improving SoC insight through on-chip diagnosis.

[BibT_eX]

[DOI]

Philipp Wagner

Subramanian Shiva Shankar

J. Syst. Archit., 2017

Region based cache coherence for tiled MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression.

[BibT_eX]

[DOI]

Pinxing Lin

Proceedings of the 18th International Conference on Parallel and Distributed Computing, 2017

Adaptive Reliability for Fault Tolerant Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Conference on Digital System Design, 2017

A non-intrusive, operating system independent spinlock profiler for embedded multicore systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions.

[BibT_eX]

[DOI]

Andreas Oeldemann

Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016

MPSoC application resilience by hardware-assisted communication virtualization.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Dark silicon management: an integrated and coordinated cross-layer approach.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

it Inf. Technol., 2016

Improving SoC Insight Through On-Chip Diagnosis.

[BibT_eX]

[DOI]

Philipp Wagner

CoRR, 2016

TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters.

[BibT_eX]

[DOI]

Ravi Kumar Pujari

Subramanian Shiva Shankar

Proceedings of the High Performance Computing - 31st International Conference, 2016

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Hardware acceleration of signature matching through multi-layer transition bit masking.

[BibT_eX]

[DOI]

Pinxing Lin

Proceedings of the 26th International Telecommunication Networks and Applications Conference, 2016

What happens on an MPSoC stays on an MPSoC - unfortunately!

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Integrated Circuits, 2016

Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip.

[BibT_eX]

[DOI]

Philipp Wagner

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

Estimation of End-to-End Packet Error Rates for NoC Multicasts.

[BibT_eX]

[DOI]

Michael Vonbun

P. Parayil Mana Damodaran

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015

Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance.

[BibT_eX]

[DOI]

J. Syst. Archit., 2015

Adaptive multi-layer techniques for increased system dependability.

[BibT_eX]

[DOI]

Johannes Maximilian Kühn

Hans-Joachim Wunderlich

Hongyan Zhang

it Inf. Technol., 2015

Sharer status-based caching in tiled multiprocessor systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Symposium on High Performance Computing, 2015

A hardware-based multi-objective thread mapper for tiled manycore architectures.

[BibT_eX]

[DOI]

Ravi Kumar Pujari

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Network Interface with Task Spawning Support for NoC-Based DSM Architectures.

[BibT_eX]

[DOI]

Jan Heißwolf

Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Fault-tolerant communication in invasive networks on chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

2014

A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs.

[BibT_eX]

[DOI]

CoRR, 2014

A network virtualization approach for performance isolation in controller area network (CAN).

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN).

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Dependable task and communication migration in tiled manycore system-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

System integration - The bridge between More than Moore and More Moore.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Performance Isolation Exposure in Virtualized Platforms with PCI Passthrough I/O Sharing.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2014, 2014

2013

Virtual networks - distributed communication resource management.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2013

Virtualized and fault-tolerant inter-layer-links for 3D-ICs.

[BibT_eX]

[DOI]

Felix Miller

Microprocess. Microsystems, 2013

Open Tiled Manycore System-on-Chip

[BibT_eX]

[DOI]

CoRR, 2013

Hardware Supported Adaptive Data Collection for Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Potentials and Challenges for Multi-Core Processors in Robotic Applications.

[BibT_eX]

[DOI]

Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

New Algorithm for Analysis of Off-target Effects in siRNA Screens.

[BibT_eX]

Proceedings of the BIOINFORMATICS 2013 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Barcelona, Spain, 11, 2013

HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation.

[BibT_eX]

[DOI]

Stefan Wallentowitz

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012

Benefits of selective packet discard in networks-on-chip.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

Multicore Enablement for Automotive Cyber Physical Systems.

[BibT_eX]

[DOI]

it Inf. Technol., 2012

System-level software performance simulation considering out-of-order processor execution.

[BibT_eX]

[DOI]

Roman Plyaskin

Proceedings of the 2012 International Symposium on System on Chip, 2012

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A framework for Open Tiled Manycore System-On-Chip.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An integrated simulation framework for invasive computing.

[BibT_eX]

[DOI]

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs.

[BibT_eX]

[DOI]

Felix Miller

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Invasive manycore architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation.

[BibT_eX]

[DOI]

Holm Rauchfuss

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011

Advanced Packet Segmentation and Buffering Algorithms in Network Processors.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2011

Accelerating collective communication in message passing on manycore System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems.

[BibT_eX]

[DOI]

Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2010, 2010

An Application-Aware Load Balancing Strategy for Network Processors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

A folded pipeline network processor architecture for 100 Gbit/s networks.

[BibT_eX]

[DOI]

Kimon Karras

Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009

Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources.

[BibT_eX]

[DOI]

Andreas Lankes

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

A Processing Path Dispatcher in Network Processor MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Improving memory subsystem performance in network processors with smart packet segmentation.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

FlexPath NP - A network processor architecture with flexible processing paths.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Network processors.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Buffer allocation for advanced packet segmentation in Network Processors.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

A Hardware Packet Re-Sequencer Unit for Network Processors.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems, 2008

System Level Simulation of Autonomic SoCs with TAPES.

[BibT_eX]

[DOI]

Andreas Lankes

Johannes Zeppenfeld

Proceedings of the Architecture of Computing Systems, 2008

2007

Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Power Estimation of Time Variant SoCs with TAPES.

[BibT_eX]

[DOI]

Andreas Lankes

Johannes Zeppenfeld

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Queuing algorithm for speculative Network Processors.

[BibT_eX]

[DOI]

Jürgen Foag

Int. J. High Perform. Comput. Netw., 2006

Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Performance evaluation for system-on-chip architectures using trace-based transaction level simulation.

[BibT_eX]

[DOI]

Rainer Ohlendorf

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Reconfigurable Processing Units vs. Reconfigurable Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

2005

TAPES - Trace-based architecture performance evaluation with SystemC.

[BibT_eX]

[DOI]

Gyoo-Yeong Lee

Des. Autom. Embed. Syst., 2005

Predictive processing architecture extension for network processors.

[BibT_eX]

[DOI]

Jürgen Foag

Proceedings of the 12th IEEE International Conference on Electronics, 2005

FlexPath NP: a network processor concept with application-driven flexible processing paths.

[BibT_eX]

[DOI]

Rainer Ohlendorf

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2003

Ein rekursives Verfahren zur Abbildung und zum Scheduling von Prozess-Graphen mit Kontrollabhängigkeiten.

[BibT_eX]

[DOI]