Frank Hannig
Orcid: 0000-0003-3663-6484Affiliations:
- University of Erlangen-Nuremberg, Germany
According to our database1,
Frank Hannig
authored at least 197 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on zbmath.org
-
on scopus.com
-
on orcid.org
-
on id.loc.gov
-
on d-nb.info
-
on dl.acm.org
On csauthors.net:
Bibliography
2024
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks.
Int. J. Parallel Program., April, 2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations.
CoRR, 2023
Proceedings of the 3rd Workshop on Machine Learning and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Concurr. Comput. Pract. Exp., 2022
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
Proceedings of the EuroMLSys '22: Proceedings of the 2nd European Workshop on Machine Learning and Systems, Rennes, France, April 5, 2022
2021
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors.
J. Signal Process. Syst., 2021
ACM Trans. Embed. Comput. Syst., 2021
J. Real Time Image Process., 2021
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021).
CoRR, 2021
*-Predictable MPSoC execution of real-time control applications using invasive computing.
Concurr. Comput. Pract. Exp., 2021
Proceedings of the SCOPES '21: 24th International Workshop on Software and Compilers for Embedded Systems, Eindhoven, The Netherlands, November 1, 2021
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2021
2020
Proceedings of the Software for Exascale Computing - SPPEXA 2016-2019, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
CoRR, 2020
Commun. ACM, 2020
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs.
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL.
Proceedings of the GPGPU@PPoPP '20: 13th Annual Workshop on General Purpose Processing using Graphics Processing Unit colocated with 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids.
Proceedings of the Euro-Par 2020: Parallel Processing Workshops, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020
2019
Trans. High Perform. Embed. Archit. Compil., 2019
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays.
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019
From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019
Computer Architecture and Design Methodologies, Springer, ISBN: 978-981-13-8387-8, 2019
2018
J. Signal Process. Syst., 2018
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays.
ACM Trans. Embed. Comput. Syst., 2018
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.
Parallel Process. Lett., 2018
J. Real Time Image Process., 2018
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs.
Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems, 2018
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
Springer, ISBN: 978-3-319-73909-0, 2018
2017
J. Signal Process. Syst., 2017
IEEE Trans. Parallel Distributed Syst., 2017
IEEE Trans. Computers, 2017
J. Syst. Archit., 2017
A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms.
Int. J. Comput. Sci. Eng., 2017
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.
Proceedings of the International Symposium on Rapid System Prototyping, 2017
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017
Hardware design and analysis of efficient loop coarsening and border handling for image processing.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2016
Proceedings of the Software for Exascale Computing - SPPEXA 2013-2015, 2016
IEEE Trans. Parallel Distributed Syst., 2016
it Inf. Technol., 2016
Hybrid code description for developing fast and resource efficient image processing architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 6th ACM SIGPLAN Workshop on X10, 2016
Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
Proceedings of the FPGAs for Software Programmers, 2016
Proceedings of the FPGAs for Software Programmers, 2016
Proceedings of the FPGAs for Software Programmers, 2016
2015
J. Syst. Archit., 2015
J. Syst. Archit., 2015
Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures.
J. Syst. Archit., 2015
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015).
CoRR, 2015
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015).
CoRR, 2015
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
J. Signal Process. Syst., 2014
J. Signal Process. Syst., 2014
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.
ACM Trans. Embed. Comput. Syst., 2014
Parallel Process. Lett., 2014
Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language.
J. Parallel Distributed Comput., 2014
CoRR, 2014
A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms.
CoRR, 2014
Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014).
CoRR, 2014
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014).
CoRR, 2014
Proceedings of the Fourth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, 2014
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014
Proceedings of the 2014 14th International Conference on Computational Science and Its Applications, Guimaraes, Portugal, June 30, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Code generation from a domain-specific language for C-based HLS of hardware accelerators.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Proceedings of the ARCS 2014, 2014
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
System integration of tightly-coupled processor arrays using reconfigurable buffer structures.
Proceedings of the Computing Frontiers Conference, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
Loop program mapping and compact code generation for programmable hardware accelerators.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012
Proceedings of the 2012 SC Companion: High Performance Computing, 2012
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging.
Proceedings of the 11th International Symposium on Parallel and Distributed Computing, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012
2011
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.
J. Low Power Electron., 2011
IEEE Embed. Syst. Lett., 2011
Resource-aware programming and simulation of MPSoC architectures through extension of X10.
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011
Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Medical Imaging 2011: Image Processing, 2011
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Decentralized dynamic resource management support for massively parallel processor arrays.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
Microprocess. Microsystems, 2009
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
J. Low Power Electron., 2009
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2009
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.
Proceedings of the ICPPW 2009, 2009
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009
Model-based synthesis and optimization of static multi-rate image processing algorithms.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.
Proceedings of the Architecture of Computing Systems, 2009
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.
Proceedings of the Architecture of Computing Systems, 2009
2008
The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.
Proceedings of the FPL 2008, 2008
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
J. Syst. Archit., 2007
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007
Massively Parallel Processor Architectures: A Co-design Approach.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
Proceedings of the Architecture of Computing Systems, 2007
2006
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology.
Int. J. Embed. Syst., 2006
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006
An Architecture Description Language for Massively Parallel Processor Architectures.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
Proceedings of the Architecture of Computing Systems, 2006
2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Defragmenting the Module Layout of a Partially Reconfigurable Device.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005
Output Serialization for FPGA-based and Coarse-grained Processor Arrays.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
2002
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002
2001
Proceedings of the Parallel Computing Technologies, 2001