Frank Hannig

According to our database1, Frank Hannig authored at least 144 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
Signal Processing Systems, 2018

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays.
ACM Trans. Embedded Comput. Syst., 2018

Automating the Development of High-Performance Multigrid Solvers.
Proceedings of the IEEE, 2018

Special issue on heterogeneous real-time image processing.
J. Real-Time Image Processing, 2018

Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs.
Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems, 2018

Automatic Kernel Fusion for Image Processing DSLs.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators.
Signal Processing Systems, 2017

Trends in Data Locality Abstractions for HPC Systems.
IEEE Trans. Parallel Distrib. Syst., 2017

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.
IEEE Trans. Computers, 2017

Introduction to the special issue on architecture of computing systems.
Journal of Systems Architecture - Embedded Systems Design, 2017

A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms.
IJCSE, 2017

Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Auto-vectorization for image processing DSLs.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Convoy tracking for ADAS on embedded GPUs.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017

Generating FPGA-based image processing accelerators with Hipacc: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

High performance network-on-chip simulation by interval-based timing predictions.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Hardware design and analysis of efficient loop coarsening and border handling for image processing.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

Efficiency in ILP processing by using orthogonality.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Systems of Partial Differential Equations in ExaSlang.
Proceedings of the Software for Exascale Computing - SPPEXA 2013-2015, 2016

HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
IEEE Trans. Parallel Distrib. Syst., 2016

Dark silicon management: an integrated and coordinated cross-layer approach.
it - Information Technology, 2016

Hybrid code description for developing fast and resource efficient image processing architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

ActorX10: an actor library for X10.
Proceedings of the 6th ACM SIGPLAN Workshop on X10, 2016

Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

FPGA-based accelerator design from a domain-specific language.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Big Data and HPC Acceleration with Vivado HLS.
Proceedings of the FPGAs for Software Programmers, 2016

HIPAcc.
Proceedings of the FPGAs for Software Programmers, 2016

FPGA Versus Software Programming: Why, When, and How?
Proceedings of the FPGAs for Software Programmers, 2016

A Quick Tour of High-Level Synthesis Solutions for FPGAs.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Synthesis and optimization of image processing accelerators using domain knowledge.
Journal of Systems Architecture - Embedded Systems Design, 2015

Resource-awareness on heterogeneous MPSoCs for image processing.
Journal of Systems Architecture - Embedded Systems Design, 2015

Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures.
Journal of Systems Architecture - Embedded Systems Design, 2015

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Invasive computing for predictable stream processing: a simulation-based case study.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures.
Proceedings of the 52nd Annual Design Automation Conference, 2015

On-demand fault-tolerant loop processing on massively parallel processor arrays.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Loop coarsening in C-based High-Level Synthesis.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Symbolic Mapping of Loop Programs onto Processor Arrays.
Signal Processing Systems, 2014

Compact Code Generation for Tightly-Coupled Processor Arrays.
Signal Processing Systems, 2014

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.
ACM Trans. Embedded Comput. Syst., 2014

Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror.
Parallel Processing Letters, 2014

Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language.
J. Parallel Distrib. Comput., 2014

ExaSlang: a domain-specific language for highly scalable multigrid solvers.
Proceedings of the Fourth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, 2014

Symbolic inner loop parallelisation for massively parallel processor arrays.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

An Evaluation of Domain-Specific Language Technologies for Code Generation.
Proceedings of the 2014 14th International Conference on Computational Science and Its Applications, Guimaraes, Portugal, June 30, 2014

An image processing library for C-based high-level synthesis.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

ExaStencils: Advanced Stencil-Code Engineering.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Code generation for embedded heterogeneous architectures on android.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Self-adaptive harris corner detector on heterogeneous many-core processor.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Code generation from a domain-specific language for C-based HLS of hardware accelerators.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Domain-specific augmentations for High-Level Synthesis.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Towards Actor-oriented Programming on PGAS-based Multicore Architectures.
Proceedings of the ARCS 2014, 2014

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
NoC simulation in heterogeneous architectures for PGAS programming model.
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Real-timerange image preprocessing on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

A prototype of an adaptive computer vision algorithm on MPSoC architecture.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

System integration of tightly-coupled processor arrays using reconfigurable buffer structures.
Proceedings of the Computing Frontiers Conference, 2013

Symbolic parallelization of loop programs for massively parallel processor arrays.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Loop program mapping and compact code generation for programmable hardware accelerators.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Hierarchical power management for adaptive tightly-coupled processor arrays.
ACM Trans. Design Autom. Electr. Syst., 2012

Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Towards Domain-Specific Computing for Stencil Codes in HPC.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging.
Proceedings of the 11th International Symposium on Parallel and Distributed Computing, 2012

Generating Device-specific GPU Code for Local Operators in Medical Imaging.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

An integrated simulation framework for invasive computing.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Power Management Strategies for Serial RapidIO Endpoints in FPGAs.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Mastering Software Variant Explosion for GPU Accelerators.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

A prototype of an invasive tightly-coupled processor array.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design of Low Power On-chip Processor Arrays.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.
J. Low Power Electronics, 2011

Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays.
Embedded Systems Letters, 2011

Resource-aware programming and simulation of MPSoC architectures through extension of X10.
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011

Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Detector defect correction of medical images on graphics processors.
Proceedings of the Medical Imaging 2011: Image Processing, 2011

Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

Distributed Resource Reservation in Massively Parallel Processor Arrays.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Decentralized dynamic resource management support for massively parallel processor arrays.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010
A deeply pipelined and parallel architecture for denoising medical images.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Compilation techniques for CGRAs: exploring all parallelization approaches.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Modeling and synthesis of communication subsystems for loop accelerator pipelines.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Scheduling Techniques for High-Throughput Loop Accelerators.
PhD thesis, 2009

A holistic approach for tightly coupled reconfigurable parallel processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
J. Low Power Electronics, 2009

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2009

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.
Proceedings of the ICPPW 2009, 2009

FPGA implementation of an invasive computing architecture.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Model-based synthesis and optimization of static multi-rate image processing algorithms.
Proceedings of the Design, Automation and Test in Europe, 2009

Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Impact of Loop Tiling on the Controller Logic of Acceleration Engines.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.
Proceedings of the Architecture of Computing Systems, 2009

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.
Proceedings of the Architecture of Computing Systems, 2009

2008
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.
Proceedings of the FPL 2008, 2008


Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Efficient control generation for mapping nested loop programs onto processor arrays.
Journal of Systems Architecture, 2007

Efficient event-driven simulation of parallel processor architectures.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Massively Parallel Processor Architectures: A Co-design Approach.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
Proceedings of the Architecture of Computing Systems, 2007

2006
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology.
IJES, 2006

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Hierarchical Partitioning for Piecewise Linear Algorithms.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

An Architecture Description Language for Massively Parallel Processor Architectures.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

A highly parameterizable parallel processor array architecture.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Controller Synthesis for Mapping Partitioned Programs on Array Architectures.
Proceedings of the Architecture of Computing Systems, 2006

2005
Automatic FIR Filter Generation for FPGAs.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Defragmenting the Module Layout of a Partially Reconfigurable Device.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Output Serialization for FPGA-based and Coarse-grained Processor Arrays.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
High-Speed Event-Driven RTL Compiled Simulation.
Proceedings of the Computer Systems: Architectures, 2004

Dynamic Piecewise Linear/Regular Algorithms.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Regular mapping for coarse-grained reconfigurable architectures.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2002
Energy estimation of nested loop programs.
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002

Generation of Distributed Loop Control.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

2001
Design Space Exploration for Massively Parallel Processor Arrays.
Proceedings of the Parallel Computing Technologies, 2001


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