Josep Rius Vázquez

According to our database1, Josep Rius Vázquez authored at least 20 papers between 1992 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2013
IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2010
A method for detecting resistive opens in buses.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Two-dimensional communication of networked devices through a single conductive surface.
Proceedings of the Seventh International Conference on Networked Sensing Systems, 2010

A single conductive surface as communication media for networked devices.
Proceedings of the 5th International ICST Conference on Body Area Networks, 2010

2009
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors.
IEEE J. Solid State Circuits, 2009

Analysis of the extra delay on interconnects caused by resistive opens and shorts.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.
Proceedings of the 14th IEEE European Test Symposium, 2009

2006
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.
J. Low Power Electron., 2006

2004
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

BIST Technique by Equally Spaced Test Vector Sequences.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Power Supply Noise Monitor for Signal Integrity Faults.
Proceedings of the 2004 Design, 2004

2003
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.
Proceedings of the Integrated Circuit and System Design, 2003

On the selection of efficient arithmetic additive test pattern generators [logic test].
Proceedings of the 8th European Test Workshop, 2003

2002
Comparison of IDDQ Testing and Very-Low Voltage Testing.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.
Proceedings of the 1999 Design, 1999

1998
IDDQ testing: state of the art and future trends.
Integr., 1998

1996
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.
J. Electron. Test., 1996

1995
Detecting I/sub DDQ/ defective CMOS circuits by depowering.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1992
Proportional BIC sensor for current testing.
J. Electron. Test., 1992


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