Salvador Manich

According to our database1, Salvador Manich authored at least 27 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact.
IEEE Access, 2022

On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

Simulation of serial RRAM cell based on a Verilog-A compact model.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

Low Cost AES Protection Against DPA Using Rolling Codes.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

A Calibratable Detector for Invasive Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2019

The Low Area Probing Detector as a Countermeasure Against Invasive Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis.
Microelectron. J., 2017

RRAM based cell for hardware security applications.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Improving security in cache memory by power efficient scrambling technique.
IET Comput. Digit. Tech., 2015

A Low Area Probing Detector for Power Efficient Security ICs.
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2014

Interleaved scrambling technique: A novel low-power security layer for cache memories.
Proceedings of the 19th IEEE European Test Symposium, 2014

A Highly Time Sensitive XOR Gate for Probe Attempt Detectors.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Differential scan-path: A novel solution for secure design-for-testability.
Proceedings of the 2013 IEEE International Test Conference, 2013

Detection of probing attempts in secure ICs.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Design and implementation of Automatic Test Equipment IP module.
Proceedings of the 15th European Test Symposium, 2010

Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electron. Test., 2004

BIST Technique by Equally Spaced Test Vector Sequences.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.
Proceedings of the Integrated Circuit and System Design, 2003

On the selection of efficient arithmetic additive test pattern generators [logic test].
Proceedings of the 8th European Test Workshop, 2003

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Low Power BIST by Filtering Non-Detecting Vectors.
J. Electron. Test., 2000

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Fault-Secure Parity Prediction Arithmetic Operators.
IEEE Des. Test Comput., 1997

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.
Proceedings of the European Design and Test Conference, 1997

Enhancing realistic fault secureness in parity prediction array arithmetic operators by I<sub>DDQ</sub> monitoring.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations.
Proceedings of the 1996 European Design and Test Conference, 1996