Rosa Rodríguez-Montañés
Orcid: 0000-0001-6231-0862Affiliations:
- Polytechnic University of Catalonia, Barcelona, Spain
According to our database1,
Rosa Rodríguez-Montañés
authored at least 45 papers
between 1991 and 2023.
Collaborative distances:
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Bibliography
2023
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs.
IEEE Access, 2023
2022
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
2016
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
2015
Proceedings of the 20th IEEE European Test Symposium, 2015
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2010
Proceedings of the 15th European Test Symposium, 2010
2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Proceedings of the 10th European Test Symposium, 2005
2004
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
On the selection of efficient arithmetic additive test pattern generators [logic test].
Proceedings of the 8th European Test Workshop, 2003
Process-variability aware delay fault testing of ΔV<sub>T</sub> and weak-open defects.
Proceedings of the 8th European Test Workshop, 2003
A Combinatorial Method for the Evaluation of Yield of Fault-Tolerant Systems-on-Chip.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003
2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
1996
J. Electron. Test., 1996
1994
Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1992
J. Electron. Test., 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1991
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991