Joseph Nahas

According to our database¹, Joseph Nahas authored at least 19 papers between 2005 and 2018.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2018

Can beyond-CMOS devices illuminate dark silicon?

[BibT_eX]

[DOI]

Commun. ACM, 2018

2016

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Analog Circuit Design Using Tunnel-FETs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Analytically Modeling Power and Performance of a CNN System.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

TFET-based Operational Transconductance Amplifier Design for CNN Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A CNN-inspired mixed signal processor based on tunnel transistors.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Nanomagnet Logic (NML).

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Nontraditional Computation Using Beyond-CMOS Tunneling Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Architectural impacts of emerging transistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Boolean circuit design using emerging tunneling devices.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Cellular neural networks for image analysis using steep slope devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Design of 3D nanomagnetic logic circuits: A full-adder case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

TFET-based cellular neural network architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Systematic design of nanomagnet logic circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Making non-volatile nanomagnet logic non-volatile.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2008

A 180 Kbit Embeddable MRAM Memory Module.

[BibT_eX]

[DOI]

Joseph J. Nahas

Thomas W. Andre

Brad Garni

Chitra K. Subramanian

IEEE J. Solid State Circuits, 2008

2007

A 180 Kbit Embeddable MRAM Memory Module.

[BibT_eX]

[DOI]

Joseph J. Nahas

Thomas W. Andre

Chitra K. Subramanian

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers.

[BibT_eX]

[DOI]

Thomas W. Andre

Joseph J. Nahas

Chitra K. Subramanian

IEEE J. Solid State Circuits, 2005

Joseph Nahas

Timeline

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