Michael T. Niemier

According to our database1, Michael T. Niemier authored at least 115 papers between 1999 and 2022.

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Bibliography

2022
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic.
IEEE Des. Test, 2022

iMARS: An In-Memory-Computing Architecture for Recommendation Systems.
CoRR, 2022

2021
Deep Random Forest with Ferroelectric Analog Content Addressable Memory.
CoRR, 2021

Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

MIMHD: Accurate and Efficient Hyperdimensional Inference Using Multi-Bit In-Memory Computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

A Flash-Based Multi-Bit Content-Addressable Memory with Euclidean Squared Distance.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

ICCAD Tutorial Session Paper Ferroelectric FET Technology and Applications: From Devices to Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

In-Memory Computing based Accelerator for Transformer Networks for Long Sequences.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and Applications.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2020

SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Algorithmic Acceleration of B/FV-like Somewhat Homomorphic Encryption for Compute-Enabled RAM.
IACR Cryptol. ePrint Arch., 2020

The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures.
IEEE Des. Test, 2020

FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric.
CoRR, 2020

GC-eDRAM design using hybrid FinFET/NC-FinFET.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Modeling and Benchmarking Computing-in-Memory for Design Space Exploration.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

AxR-NN: Approximate Computation Reuse for Energy-Efficient Convolutional Neural Networks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Emerging Neural Workloads and Their Impact on Hardware.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Ultra-Dense 2FeFET TCAM Design Based on a Multi-Domain FeFET Model.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Mixed Signal Architecture for Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2019

A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies.
IEEE Des. Test, 2019

Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies.
IEEE Des. Test, 2019

Nonvolatile Spintronic Memory Cells for Neural Networks.
CoRR, 2019

Application-level Studies of Cellular Neural Network-based Hardware Accelerators.
CoRR, 2019

Ferroelectric FET Based TCAM Designs for Energy Efficient Computing.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Uniform Modeling Methodology for Benchmarking DNN Accelerators.
Proceedings of the International Conference on Computer-Aided Design, 2019

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

Ferroelectric FET Based In-Memory Computing for Few-Shot Learning.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design of Hardware-Friendly Memory Enhanced Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt.
Frontiers Inf. Technol. Electron. Eng., 2018

Can beyond-CMOS devices illuminate dark silicon?
Commun. ACM, 2018

Computing in memory with FeFETs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Nonvolatile Lookup Table Design Based on Ferroelectric Field-Effect Transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and optimization of FeFET-based crossbars for binary convolution neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Computing with ferroelectric FETs: Devices, models, systems, and applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Biomedical Image Segmentation Using Fully Convolutional Networks on TrueNorth.
Proceedings of the 31st IEEE International Symposium on Computer-Based Medical Systems, 2018

2017
Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.
IEEE Trans. Emerg. Top. Comput., 2017

Exploiting Non-Volatility for Information Processing.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design and benchmarking of ferroelectric FET based TCAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Advanced spintronic memory and logic for non-volatile processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cellular neural network friendly convolutional neural networks - CNNs with CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Emerging Technology-Based Design of Primitives for Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., 2016

Molecular cellular networks: A non von Neumann architecture for molecular electronics.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Enhancing Hardware Security with Emerging Transistor Technologies.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Design of latches and flip-flops using emerging tunneling devices.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Using emerging technologies for hardware security beyond PUFs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Analog Circuit Design Using Tunnel-FETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Analytically Modeling Power and Performance of a CNN System.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

TFET-based Operational Transconductance Amplifier Design for CNN Systems.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A CNN-inspired mixed signal processor based on tunnel transistors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Towards systematic design of 3D pNML layouts.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Nanomagnet Logic (NML).
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Nontraditional Computation Using Beyond-CMOS Tunneling Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Understanding the landscape of accelerators for vision.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Architectural impacts of emerging transistors.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Boolean circuit design using emerging tunneling devices.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Cellular neural networks for image analysis using steep slope devices.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Design of 3D nanomagnetic logic circuits: A full-adder case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
TFET-based cellular neural network architectures.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Systematic design of nanomagnet logic circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Minimum-energy state guided physical design for nanomagnet logic.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

GPU acceleration of Data Assembly in Finite Element Methods and its energy implications.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
A Reconfigurable PLA Architecture for Nanomagnet Logic.
ACM J. Emerg. Technol. Comput. Syst., 2012

Network on metachip architectures.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Making non-volatile nanomagnet logic non-volatile.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Performance and Energy Impact of Locally Controlled NML Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2011

2010
Design and comparison of NML systolic architectures.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

2009
Defects and faults in QCA-based PLAs.
ACM J. Emerg. Technol. Comput. Syst., 2009

System-level energy and performance projections for nanomagnet-based logic.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Molecular QCA design with chemically reasonable constraints.
ACM J. Emerg. Technol. Comput. Syst., 2008

Defect tolerance in QCA-based PLAs.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Bridging the gap between nanomagnetic devices and circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Design and defect tolerance beyond CMOS.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Fabricatable Interconnect and Molecular QCA Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Approximating the Maximum Sharing Problem.
Proceedings of the Algorithms and Data Structures, 10th International Workshop, 2007

Clocking structures and power analysis for nanomagnet-based logic devices.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Fault Models and Yield Analysis for QCA-based PLAs.
Proceedings of the FPL 2007, 2007

2006
PLAs in Quantum-dot Cellular Automata.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Using CAD to shape experiments in molecular QCA.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
Partitioning and placement for buildable QCA circuits.
ACM J. Emerg. Technol. Comput. Syst., 2005

Automatic cell placement for quantum-dot cellular automata.
Integr., 2005

Eliminating wire crossings for molecular quantum-dot cellular automata implementation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Using Circuits and Systems-Level Research to Drive Nanotechnology.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Automatic cell placement for quantum-dot cellular automata.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions.
Proceedings of the 41th Design Automation Conference, 2004

2002
Teaching students computer architecture for new, nanotechnologies.
Proceedings of the 2002 workshop on Computer architecture education, 2002

2001
Problems in designing with QCAs: Layout = Timing.
Int. J. Circuit Theory Appl., 2001

Petaflop Computing for Protein Folding.
Proceedings of the Tenth SIAM Conference on Parallel Processing for Scientific Computing, 2001

Exploring and exploiting wire-level pipelining in emerging technologies.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
A design of and design tools for a novel quantum dot based microprocessor.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Logic in wire: using quantum dots to implement a microprocessor.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


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