Joshua Adiel Wijaya

According to our database, Joshua Adiel Wijaya authored at least 3 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

High-Accuracy, Low-Utilization Multichannel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multidimensional Delay Array.

Poki Chen, Joshua Adiel Wijaya, Chen Chen, Xiaoqing Wen, Stefan Holst

IEEE Trans. Very Large Scale Integr. Syst., June, 2026

2024

Area Efficient 0.009-mm² 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator.

Joshua Adiel Wijaya, Poki Chen, Lucky Kumar Pradhan, Ahmad Shahid Bhatti, Seiji Kajihara

IEEE Trans. Very Large Scale Integr. Syst., October, 2024

2022

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection.

Poki Chen, Joshua Adiel Wijaya, Seiji Kajihara, Trio Adiono, Hsiang-Yu Chen, Ruei-Ting Wang, Yousuke Miyake

IEEE Access, 2022