Jun Yuan

Affiliations:
  • Atrenta, Inc., San José, CA, USA


According to our database1, Jun Yuan authored at least 13 papers between 1996 and 2006.

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Bibliography

2006
Constraint-based verification.
Springer, ISBN: 978-0-387-25947-5, 2006

2004
Simplifying Boolean constraint solving for random simulation-vector generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
A Framework for Constrained Functional Verification.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Constraint synthesis for environment modeling in functional verification.
Proceedings of the 40th Design Automation Conference, 2003

2002
A Method for Synthesizing Boolean Constrains.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Simplifying Constraint Solving in Random Simulation Generation.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001
Efficient control state-space search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
Automatic Vector Generation Using Constraints and Biasing.
J. Electron. Test., 2000

1999
Integrated Formal and Informal Design Verification of Commercial Integrated Circuits.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Modeling design constraints and biasing in simulation using BDDs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Approximate reachability don't cares for CTL model checking.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
On Combining Formal and Informal Verification.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996
Commercial Design Verification: Methodology and Tools.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


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