# Adnan Aziz

According to our database

Collaborative distances:

^{1}, Adnan Aziz authored at least 90 papers between 1994 and 2018.Collaborative distances:

## Timeline

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## Bibliography

2018

Application of Visual Analysis to Detect and Analyze Patterns in VoIP Attack Traffic.

Proceedings of the 17th IEEE International Conference On Trust, 2018

Classification of SIP Attack Variants with a Hybrid Self-enforcing Network.

Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018

2016

Symbolic Model Checking.

Encyclopedia of Algorithms, 2016

Binary Decision Graph.

Encyclopedia of Algorithms, 2016

2015

Global VoIP security threats - large scale validation based on independent honeynets.

Proceedings of the 14th IFIP Networking Conference, 2015

2014

A distributed infrastructure to analyse SIP attacks in the Internet.

Proceedings of the 2014 IFIP Networking Conference, Trondheim, 2014

2013

Development and Analysis of Generic VoIP Attack Sequences Based on Analysis of Real Attack Traffic.

Proceedings of the 12th IEEE International Conference on Trust, 2013

2009

TuneLogic: Post-silicon tuning of dual-Vdd designs.

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Symbolic Model Checking.

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Binary Decision Graph.

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Adaptive SRAM memory for low power and high yield.

Proceedings of the 26th International Conference on Computer Design, 2008

Optimal Constraint-Preserving Netlist Simplification.

Proceedings of the Formal Methods in Computer-Aided Design, 2008

TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.

Proceedings of the 45th Design Automation Conference, 2008

2007

Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies

CoRR, 2007

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.

Proceedings of the IFIP VLSI-SoC 2007, 2007

Implementing DSP Algorithms with On-Chip Networks.

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions.

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Sequential circuits for program analysis.

Proceedings of the 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007), 2007

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations.

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Sequential Circuits for Relational Analysis.

Proceedings of the 29th International Conference on Software Engineering (ICSE 2007), 2007

Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine.

Proceedings of the 25th International Conference on Computer Design, 2007

Global Optimization of Compositional Systems.

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006

Cache Organization for Embeded Processors: CAM-vs-SRAM.

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation.

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Scheduling Traffic Matrices On General Switch Fabrics.

Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006

Constraint-based verification.

Springer, ISBN: 978-0-387-25947-5, 2006

2005

Scalable compositional minimization via static analysis.

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Exploiting Constraints in Transformation-Based Verification.

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

Simplifying Boolean constraint solving for random simulation-vector generation.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Randomized Parallel Schedulers for Switch-Memory-Switch Routers: Analysis and Numerical Studies.

Proceedings of the Proceedings IEEE INFOCOM 2004, 2004

Synthesizing interconnect-efficient low density parity check codes.

Proceedings of the 41th Design Automation Conference, 2004

2003

Sequential optimization in the absence of global reset.

ACM Trans. Design Autom. Electr. Syst., 2003

A high-performance architecture and BDD-based synthesis methodology for packet classification.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.

Formal Methods in System Design, 2003

An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.

Formal Methods in System Design, 2003

A near optimal scheduler for switch-memory-switch routers.

Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

A Framework for Constrained Functional Verification.

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Constraint synthesis for environment modeling in functional verification.

Proceedings of the 40th Design Automation Conference, 2003

2002

Formula-Dependent Equivalence for Compositional CTL Model Checking.

Formal Methods in System Design, 2002

Improved SAT-Based Bounded Reachability Analysis.

Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Method for Synthesizing Boolean Constrains.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Simplifying Constraint Solving in Random Simulation Generation.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Proceedings of the Proceedings IEEE INFOCOM 2002, 2002

A Middle Ground between CAMs and DAGs for High-Speed Packet Classification.

Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

Multicast Scheduling for Switches with Multiple Input-Queues.

Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

2001

Optimizing designs containing black boxes.

ACM Trans. Design Autom. Electr. Syst., 2001

Buffer minimization in pass transistor logic.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Theory of safe replacements for sequential circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Efficient control state-space search.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

SIVA: A System for Coverage-Directed State Space Search.

J. Electronic Testing, 2001

OC-3072 packet classification using BDDs and pipelined SRAMs.

Proceedings of the Ninth Symposium on High Performance Interconnects, 2001

Rarity based guided state space search.

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Integrated power supply planning and floorplanning.

Proceedings of ASP-DAC 2001, 2001

2000

Model-checking continous-time Markov chains.

ACM Trans. Comput. Log., 2000

Simultaneous routing and buffer insertion with restrictions onbuffer locations.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Sequential synthesis using S1S.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Automatic Vector Generation Using Constraints and Biasing.

J. Electronic Testing, 2000

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.

Proceedings of the 2000 International Symposium on Physical Design, 2000

Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Automatic Lighthouse Generation for Directed State Space Search.

Proceedings of the 2000 Design, 2000

Meeting Delay Constraints in DSM by Minimal Repeater Insertion.

Proceedings of the 2000 Design, 2000

An Abstraction Algorithm for the Verification of Generalized C-Slow Designs.

Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999

Equivalences for Fair Kripke Structures.

Chicago J. Theor. Comput. Sci., 1999

Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking.

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Performance Driven Synthesis for Pass-Transistor Logic.

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.

Proceedings of the IEEE International Conference On Computer Design, 1999

Modeling design constraints and biasing in simulation using BDDs.

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.

Proceedings of the 36th Conference on Design Automation, 1999

Enhancing Simulation with BDDs and ATPG.

Proceedings of the 36th Conference on Design Automation, 1999

Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists.

Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998

Area-oriented synthesis for pass-transistor logic.

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Techniques for Implicit State Enumeration of EFSMs.

Proceedings of the Formal Methods in Computer-Aided Design, 1998

Hybrid Techniques for Fast Functional Simulation.

Proceedings of the 35th Conference on Design Automation, 1998

Hybrid Verification Using Saturated Simulation.

Proceedings of the 35th Conference on Design Automation, 1998

1997

Sequential optimisation without state space exploration.

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Optimizing Designs Containing Black Boxes.

Proceedings of the 34st Conference on Design Automation, 1997

On Combining Formal and Informal Verification.

Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996

VIS.

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

VIS: A System for Verification and Synthesis.

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

Verifying Continuous Time Markov Chains.

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Exploiting power-up delay for sequential optimization.

Proceedings of the Proceedings EURO-DAC'95, 1995

It Usually Works: The Temporal Logic of Stochastic Systems.

Proceedings of the Computer Aided Verification, 1995

Supervisory Control of Finite State Machines.

Proceedings of the Computer Aided Verification, 1995

1994

Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment.

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Multi-level synthesis for safe replaceability.

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

BDD Variable Ordering for Interacting Finite State Machines.

Proceedings of the 31st Conference on Design Automation, 1994

HSIS: A BDD-Based Environment for Formal Verification.

Proceedings of the 31st Conference on Design Automation, 1994

Formula-Dependent Equivalence for Compositional CTL Model Checking.

Proceedings of the Computer Aided Verification, 6th International Conference, 1994