Kamlesh Singh

Orcid: 0000-0002-2639-6053

According to our database1, Kamlesh Singh authored at least 14 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

2021
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Twenty Years of Near/Sub-Threshold Design Trends and Enablement.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection.
IEEE Trans. Biomed. Circuits Syst., 2021

A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Management of Unpredictable Harvested-Energy IoT Devices.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Standard Cell based Memory Compiler for Near/Sub-threshold Operation.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
Analysis and Modeling of Chopping Phase Non-Overlap in Continuous-Time ΔΣ Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low power latch based design with smart retiming.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016


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