Roel Jordans

According to our database1, Roel Jordans authored at least 37 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

2022
Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware.
IEEE Access, 2022

Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Management of Unpredictable Harvested-Energy IoT Devices.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

NMPO: Near-Memory Computing Profiling and Offloading.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
PR<sup>3</sup>: A system For radio-interferometry and radiation measurement on sounding rockets.
Microprocess. Microsystems, 2020

An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Near Memory Acceleration on High Resolution Radio Astronomy Imaging.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

PET-to-MLIR: A polyhedral front-end for MLIR.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

TDO-CIM: Transparent Detection and Offloading for Computation In-memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Near-memory computing: Past, present, and future.
Microprocess. Microsystems, 2019

Towards Efficient Code Generation for Exposed Datapath Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

Memory and Parallelism Analysis Using a Platform-Independent Approach.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

Platform Independent Software Analysis for Near Memory Computing.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Determining the necessity of fault tolerance techniques in FPGA devices for space missions.
Microprocess. Microsystems, 2018

Fast and Portable Vector DSP Simulation Through Automatic Vectorization.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

A Review of Near-Memory Computing Architectures: Opportunities and Challenges.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Extending Halide to Improve Software Development for Imaging DSPs.
ACM Trans. Archit. Code Optim., 2017

Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project.
Microprocess. Microsystems, 2017

Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
High-level software-pipelining in LLVM.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths.
Microprocess. Microsystems, 2014

Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

Construction and exploitation of VLIW asips with multiple vector-widths.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocess. Microsystems, 2013

Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Exploring processor parallelism: Estimation methods and optimization strategies.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
An Automated Flow to Map Throughput Constrained Applications to a MPSoC.
Proceedings of the Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011


  Loading...