Hamed Fatemi

According to our database1, Hamed Fatemi authored at least 25 papers between 2005 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.
IEEE Trans. VLSI Syst., 2019

Enhancing sensitivity-based power reduction for an industry IC design context.
Integr., 2019

Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs.
Integr., 2019

Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.
IEEE Trans. Computers, 2018

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Low power latch based design with smart retiming.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Logic Design Partitioning for Stacked Power Domains.
IEEE Trans. VLSI Syst., 2017

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.
Microprocess. Microsystems, 2017

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling.
J. Solid-State Circuits, 2017

A scan-chain based state retention methodology for IoT processors operating on intermittent energy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Floorplan and placement methodology for improved energy reduction in stacked power-domain design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A microcontroller with 96% power-conversion efficiency using stacked voltage domains.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Circuit valorization in the IC design ecosystem.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Lower power by voltage stacking: a fine-grained system design approach.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Supervised learning based model for predicting variability-induced timing errors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Digital Systems Power Management for High Performance Mixed Signal Platforms.
IEEE Trans. on Circuits and Systems, 2014

Sliding-Mode Control to Compensate PVT Variations in dual core systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DC-SIMD : Dynamic communication for SIMD processors.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications.
J. Embedded Computing, 2006

Run-time reconfiguration of communication in SIMD architectures.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Dynamic-SIMD for lens distortion compensation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2005