Jos Huisken

According to our database1, Jos Huisken authored at least 78 papers between 1986 and 2022.

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Bibliography

2022
Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection.
IEEE Trans. Biomed. Circuits Syst., 2021

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality.
J. Electron. Test., 2021

2020
An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Standard Cell based Memory Compiler for Near/Sub-threshold Operation.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults.
Proceedings of the IEEE European Test Symposium, 2020

Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Defect-Location Identification for Cell-Aware Test.
Proceedings of the IEEE Latin American Test Symposium, 2019

Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library.
Proceedings of the IEEE International Test Conference, 2019

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices.
Proceedings of the IEEE International Test Conference in Asia, 2019

An Automated Approximation Methodology for Arithmetic Circuits.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Low power latch based design with smart retiming.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Designing Energy Efficient Approximate Multipliers for Neural Acceleration.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Reconfigurable Support Vector Machine Classifier with Approximate Computing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2014
A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications.
IEEE Trans. Biomed. Circuits Syst., 2014

2013
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems.
J. Signal Process. Syst., 2013

Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors.
IEEE Micro, 2012

Memory-aware system scenario approach energy impact.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Standard cell sizing for subthreshold operation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Sub-word Handling in Data-parallel Mapping.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
A 36μW heartbeat-detection processor for a wireless sensor node.
ACM Trans. Design Autom. Electr. Syst., 2011

A 2.4 GHz ULP OOK Single-Chip Transceiver for Healthcare Applications.
IEEE Trans. Biomed. Circuits Syst., 2011

An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold.
IEEE Trans. Biomed. Circuits Syst., 2011

Sub-threshold synchronizer.
Microelectron. J., 2011

A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy.
IEEE J. Solid State Circuits, 2011

A Lightweight Security Scheme for Wireless Body Area Networks: Design, Energy Evaluation and Proposed Microprocessor Design.
J. Medical Syst., 2011

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A 2.4GHz ULP OOK single-chip transceiver for healthcare applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A dual-core system solution for wearable health monitors.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

The impact of inverse narrow width effect on sub-threshold device sizing.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Energy efficient computation with self-adaptive single-ended body bias.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Energy Efficiency Using Loop Buffer based Instruction Memory Organizations.
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010

Circuits for portable medical electronic systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Automatic synthesis of near-threshold circuits with fine-grained performance tunability.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Exploration of cryptographic ASIP designs for wireless sensor nodes.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Novel wide voltage range level shifter for near-threshold designs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

The challenges of implementing fine-grained power gating.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Extending Synchronization from Super-Threshold to Sub-threshold Region.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring.
J. Signal Process. Syst., 2009

CoMPSoC: A template for composable and predictable multi-processor system on chips.
ACM Trans. Design Autom. Electr. Syst., 2009

Ultra-Low Power Sensor Design for Wireless Body Area Networks - Challenges, Potential Solutions, and Applications.
J. Digit. Content Technol. its Appl., 2009

2008
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

2007
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Integrating VLIW Processors with a Network on Chip.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Power Distribution and Management.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Ultra Low Power ASIP Design for Wireless Sensor Nodes.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A multistandard FFT processor for wireless system-on-chip implementations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver.
Proceedings of the 2004 Design, 2004

A Scalable Architecture for LDPC Decodin.
Proceedings of the 2004 Design, 2004

2003
AVISPA: a massively parallel reconfigurable accelerator.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002
Breaking an application specific instruction-set processor: the first step towards embedded software testing.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Guest editorial.
IEEE J. Solid State Circuits, 2001

Power-efficient layered turbo decoder processor.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Numerical Accuracy of Fast Fourier Transforms with CORDIC Arithmetic.
J. VLSI Signal Process., 2000

1999
Components for hand-held multimedia devices.
Proceedings of the Third IEEE Workshop on Multimedia Signal Processing, 1999

1996
FADIC: Architectural Synthesis applied in IC Design.
Proceedings of the 33st Conference on Design Automation, 1996

1993
Synthesis of synchronous communication hardware in a multiprocessor architecture.
J. VLSI Signal Process., 1993

1991
PHIDEO: a silicon compiler for high speed algorithms.
Proceedings of the conference on European design automation, 1991

1990
An integrated automatic design system for complex DSP algorithms.
J. VLSI Signal Process., 1990

1986
On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011.
Proceedings of the IEEE International Conference on Acoustics, 1986


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