Kan Xiao

According to our database1, Kan Xiao authored at least 15 papers between 2012 and 2017.

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Bibliography

2017
Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Hardware Trojans: Lessons Learned after One Decade of Research.
ACM Trans. Design Autom. Electr. Syst., 2016

Security Rule Checking in IC Design.
Computer, 2016

AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Efficient and secure split manufacturing via obfuscated built-in self-authentication.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

DRAM based Intrinsic Physical Unclonable Functions for System Level Security.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Bit selection algorithm suitable for high-volume production of SRAM-PUF.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

TI-TRNG: Technology Independent True Random Number Generator.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Advanced Analysis of Cell Stability for Reliable SRAM PUFs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay.
IEEE Des. Test, 2013

A study on the effectiveness of Trojan detection techniques using a red team blue team approach.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

BISA: Built-in self-authentication for preventing hardware Trojan insertion.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

2012
A zero-overhead IC identification technique using clock sweeping and path delay analysis.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Path-delay fingerprinting for identification of recovered ICs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012


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