Adib Nahiyan

According to our database, Adib Nahiyan authored at least 14 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.

M. Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2021

2020

SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.

Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2020

Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation.

Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2020

A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding.

Huanyu Wang, Qihang Shi, Adib Nahiyan, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment.

Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.

Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.

M. Sazadur Rahman, Adib Nahiyan, Sarah Amir, Fahim Rahman, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2019

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.

Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark M. Tehranipoor

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection.

Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark M. Tehranipoor, Martin Swany

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

2017

Hardware trojan detection through information flow security verification.

Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2017

Standardizing Bad Cryptographic Practice: A Teardown of the IEEE Standard for Protecting Electronic-design Intellectual Property.

Animesh Chhotaray, Adib Nahiyan, Thomas Shrimpton, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.

Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Security Rule Checking in IC Design.

Kan Xiao, Adib Nahiyan, Mark M. Tehranipoor

Computer, 2016

AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs.

Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark M. Tehranipoor

Proceedings of the 53rd Annual Design Automation Conference, 2016